參數(shù)資料
型號: GS8161Z32D-250IT
廠商: Electronic Theatre Controls, Inc.
英文描述: 10-Bit Voltage Clamp 24-TVSOP -40 to 85
中文描述: 35.7流水線和流量,通過同步唑的SRAM
文件頁數(shù): 23/36頁
文件大小: 939K
代理商: GS8161Z32D-250IT
GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 2.15 11/2004
23/36
1998, GSI Technology
Flow Through Mode Timing
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V
DD
. The JTAG output
drivers are powered by V
DDQ
.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either V
DD
or V
SS
. TDO should be left unconnected.
Write A
Write B
Write B+1
Read C
Cont
Read D
Write E
Read F
Write G
D(A)
D(B)
D(B+1)
Q(C)
Q(D)
D(E)
Q(F)
D(G)
tOLZ
tOE
tOHZ
tKQX
tKQ
tLZ
tHZ
tKQX
tKQ
tLZ
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tKC
tKL
tKH
A
B
C
D
E
F
G
*Note: E = High(False) if E1 = 1 or E2 = 0 or E3 = 1
CK
CKE
E
ADV
W
Bn
A0–An
DQ
G
相關PDF資料
PDF描述
GS8161Z32D-250T 10-Bit Voltage Clamp 24-TVSOP -40 to 85
GS8161Z32T-133 10-Bit Voltage Clamp 24-TVSOP -40 to 85
GS8161Z32T-133I 10-Bit Voltage Clamp 24-SOIC -40 to 85
GS8161Z32T-133IT 10-Bit Voltage Clamp 24-SOIC -40 to 85
GS8161Z32T-133T 10-Bit Voltage Clamp 24-SOIC -40 to 85
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