參數(shù)資料
型號(hào)： GS8161Z32BGD-200V
廠商： GSI TECHNOLOGY
元件分類： DRAM
英文描述： 18Mb Pipelined and Flow Through Synchronous NBT SRAM
中文描述： 512K X 32 ZBT SRAM, 6.5 ns, PBGA165
封裝： 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
文件頁(yè)數(shù)： 14/35頁(yè)
文件大?。?/td> 790K
代理商： GS8161Z32BGD-200V
GS8161ZxxB(T/D)-xxxV
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01a 6/2006
14/35
2004, GSI Technology
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
Mode Pin Functions
Mode Name
Pin Name
State
L
H
L
H or NC
L or NC
Function
Linear Burst
Interleaved Burst
Flow Through
Pipeline
Active
Standby, I
DD
= I
SB
Dual Cycle Deselect
Single Cycle Deselect
High Drive (Low Impedance)
Low Drive (High Impedance)
Burst Order Control
LBO
Output Register Control
FT
Power Down Control
ZZ
H
Single/Dual Cycle Deselect Control
SCD
L
H or NC
L
H or NC
FLXDrive Output Impedance Control
ZQ
Note:
There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in
the default states as specified in the above table.
There are pull-up devices on the ZQ and SCD pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip
will operate in the default states as specified in the above tables.
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