參數(shù)資料
型號(hào)： GS8161Z32BGD-150V
廠商： GSI TECHNOLOGY
元件分類： DRAM
英文描述： 18Mb Pipelined and Flow Through Synchronous NBT SRAM
中文描述： 512K X 32 ZBT SRAM, 7.5 ns, PBGA165
封裝： 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
文件頁(yè)數(shù)： 23/35頁(yè)
文件大?。?/td> 790K
代理商： GS8161Z32BGD-150V
GS8161ZxxB(T/D)-xxxV
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01a 6/2006
23/35
2004, GSI Technology
Flow Through Mode Timing (NBT)
Write A
Write B
Write B+1
Read C
Cont
Read D
Write E
Read F
Write G
D(A)
D(B)
D(B+1)
Q(C)
Q(D)
D(E)
Q(F)
D(G)
tOLZ
tOE
tOHZ
tKQX
tKQ
tLZ
tHZ
tKQX
tKQ
tLZ
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tKC
tKL
tKH
A
B
C
D
E
F
G
*Note: E = High(False) if E1 = 1 or E2 = 0 or E3 = 1
CK
CKE
E*
ADV
W
Bn
A0–An
DQ
G
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V
DD
. The JTAG output
drivers are powered by V
DDQ
.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either V
DD
or V
SS
. TDO should be left unconnected.
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