- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄383027 > GS8161Z32BD-150IV (GSI TECHNOLOGY) 18Mb Pipelined and Flow Through Synchronous NBT SRAM PDF資料下載
參數(shù)資料
| 型號(hào)： | GS8161Z32BD-150IV |
| 廠商： | GSI TECHNOLOGY |
| 元件分類(lèi)： | DRAM |
| 英文描述： | 18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| 中文描述： | 512K X 32 ZBT SRAM, 7.5 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1 MM PITCH, FPBGA-165 |
| 文件頁(yè)數(shù)： | 21/35頁(yè) |
| 文件大?。?/td> | 790K |
| 代理商： | GS8161Z32BD-150IV |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)當(dāng)前第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)
AC Electrical Characteristics
Parameter
Symbol
-250
-200
-150
Unit
Min
Max
Min
Max
Min
Max
Pipeline
Clock Cycle Time
tKC
4.0
—
5.0
—
6.7
—
ns
Clock to Output Valid
tKQ
—
3.0
—
3.0
—
3.8
ns
Clock to Output Invalid
tKQX
1.5
—
1.5
—
1.5
—
ns
Clock to Output in Low-Z
tLZ
1
1.5
—
1.5
—
1.5
—
ns
Setup time
tS
1.4
—
1.4
—
1.5
—
ns
Hold time
tH
0.2
—
0.4
—
0.5
—
ns
Flow Through
Clock Cycle Time
tKC
5.5
—
6.5
—
7.5
—
ns
Clock to Output Valid
tKQ
—
5.5
—
6.5
—
7.5
ns
Clock to Output Invalid
tKQX
2.0
—
2.0
—
2.0
—
ns
Clock to Output in Low-Z
tLZ
1
2.0
—
2.0
—
2.0
—
ns
Setup time
tS
1.5
—
1.5
—
1.5
—
ns
Hold time
tH
0.5
—
0.5
—
0.5
—
ns
Clock HIGH Time
tKH
1.3
—
1.3
—
1.5
—
ns
Clock LOW Time
tKL
1.7
—
1.7
—
1.7
—
ns
Clock to Output in
High-Z
tHZ
1
1.5
2.5
1.5
3.0
1.5
3.0
ns
G to Output Valid
tOE
—
2.5
—
3.0
—
3.8
ns
G to output in Low-Z
tOLZ
1
0
—
0
—
0
—
ns
G to output in High-Z
tOHZ
1
—
2.5
—
3.0
—
3.8
ns
ZZ setup time
tZZS
2
5
—
5
—
5
—
ns
ZZ hold time
tZZH
2
1
—
1
—
1
—
ns
ZZ recovery
tZZR
20
—
20
—
20
—
ns
GS8161ZxxB(T/D)-xxxV
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.01a 6/2006
21/35
2004, GSI Technology
Notes:
1.
2.
These parameters are sampled and are not 100% tested.
ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS8161Z32BD-150V | 18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8161Z32BD-200IV | 18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8161Z32BD-200V | 18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8161Z32BD-250IV | 18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8161Z32BD-250V | 18Mb Pipelined and Flow Through Synchronous NBT SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS8161Z32BD-150V | 制造商:GSI 制造商全稱:GSI Technology 功能描述:18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8161Z32BD-200 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8161Z32BD-200I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8161Z32BD-200IV | 制造商:GSI 制造商全稱:GSI Technology 功能描述:18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8161Z32BD-200V | 制造商:GSI 制造商全稱:GSI Technology 功能描述:18Mb Pipelined and Flow Through Synchronous NBT SRAM |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。