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參數(shù)資料
| 型號： | GS8161Z18D-166 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 13-Bit to 26-Bit Registered Buffer with SSTL_2 Inputs and Outputs 56-VQFN 0 to 70 |
| 中文描述： | 35.7流水線和流量，通過同步唑的SRAM |
| 文件頁數(shù)： | 13/36頁 |
| 文件大小： | 939K |
| 代理商： | GS8161Z18D-166 |
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GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 2.15 11/2004
13/36
1998, GSI Technology
Flow Through Mode Data I/O State Diagram
High Z
(Data In)
Data Out
(Q Valid)
High Z
B W
B
R
B
D
R
W
R
W
D
D
Current State (n)
Next State (n+1)
Transition
Input Command Code
Key
Notes:
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Clock (CK)
Command
Current State
Next State
n
n+1
n+2
n+3
Current State and Next State Definition for:
Pipeline and Flow through Read Write Control State Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS8161Z18D-166I | 13-Bit to 26-Bit Registered Buffer with SSTL_2 Inputs and Outputs 56-VQFN 0 to 70 |
| GS8161Z18D-166IT | 24-Bit to 48-Bit Registered Buffer with SSTL_2 Inputs and Outputs 114-BGA MICROSTAR 0 to 70 |
| GS8161Z18D-166T | 24-Bit to 48-Bit Registered Buffer with SSTL_2 Inputs and Outputs 114-LFBGA 0 to 70 |
| GS8161Z18D-200 | 18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8161Z18D-200I | 18Mb Pipelined and Flow Through Synchronous NBT SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS8161Z18D-166I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8161Z18D-166IT | 制造商:GSI 制造商全稱:GSI Technology 功能描述:18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8161Z18D-166T | 制造商:GSI 制造商全稱:GSI Technology 功能描述:18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8161Z18D-200 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:18Mb Pipelined and Flow Through Synchronous NBT SRAM |
| GS8161Z18D-200I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:18Mb Pipelined and Flow Through Synchronous NBT SRAM |
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