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參數資料
| 型號： | GS8161E18D-225I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Quad 2-input Exclusive-OR gates 14-SOIC 0 to 70 |
| 中文描述： | 100萬× 18，512k × 32的，為512k × 36 35.7同步突發(fā)靜態(tài)存儲器 |
| 文件頁數： | 14/36頁 |
| 文件大?。?/td> | 939K |
| 代理商： | GS8161E18D-225I |
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GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 2.15 11/2004
14/36
1998, GSI Technology
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
Mode Pin Functions
Note:
There are pull-up devices on the FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate
in the default states as specified in the above tables.
Burst Counter Sequences
BPR 1999.05.18
Mode Name
Pin
Name
State
Function
Burst Order Control
LBO
L
H
Linear Burst
Interleaved Burst
Active
Standby, I
DD
= I
SB
Power Down Control
ZZ
L or NC
H
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
相關PDF資料 |
PDF描述 |
|---|---|
| GS8161E18D-250 | Quad 2-input Exclusive-OR gates 14-SOIC 0 to 70 |
| GS8161E18D-250I | Quad 2-input Exclusive-OR gates 14-SOIC 0 to 70 |
| GS8161E18T-133 | Quad 2-input Exclusive-OR gates 14-SOIC 0 to 70 |
| GS8161E36D-225I | 25-Bit Configurable Registered Buffer With Address-Parity Test 96-LFBGA 0 to 70 |
| GS8161E36D-250 | 1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs |
相關代理商/技術參數 |
參數描述 |
|---|---|
| GS8161E18D-250 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs |
| GS8161E18D-250I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs |
| GS8161E18DD-150 | 制造商:GSI Technology 功能描述:165 BGA - Bulk |
| GS8161E18DD-200 | 制造商:GSI Technology 功能描述:165 BGA - Bulk |
| GS8161E18DD-250 | 制造商:GSI Technology 功能描述:165 BGA - Bulk |
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