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參數(shù)資料
| 型號(hào)： | GS8161E18D-225 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Quad 2-input Exclusive-OR gates 14-SOIC 0 to 70 |
| 中文描述： | 100萬× 18，512k × 32的，為512k × 36 35.7同步突發(fā)靜態(tài)存儲(chǔ)器 |
| 文件頁數(shù)： | 21/36頁 |
| 文件大?。?/td> | 939K |
| 代理商： | GS8161E18D-225 |
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GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D)
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 2.15 11/2004
21/36
Notes:
1.
2.
These parameters are sampled and are not 100% tested.
ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
AC Electrical Characteristics
Parameter
Symbol
-250
-225
-200
-166
-150
-133
Unit
Min
4.0
—
1.5
Max
—
2.5
—
Min
4.4
—
1.5
Max
—
2.7
—
Min
5.0
—
1.5
Max
—
3.0
—
Min
6.0
—
1.5
Max
—
3.4
—
Min
6.7
—
1.5
Max
—
3.8
—
Min
7.5
—
1.5
Max
—
4.0
—
Pipeline
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
tKC
tKQ
tKQX
ns
ns
ns
Clock to Output in Low-Z
tLZ
1
tS
tH
tKC
tKQ
tKQX
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
1.5
—
ns
Setup time
Hold time
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
1.2
0.2
5.5
—
3.0
—
—
—
5.5
—
1.3
0.3
6.0
—
3.0
—
—
—
6.0
—
1.4
0.4
6.5
—
3.0
—
—
—
6.5
—
1.5
0.5
7.0
—
3.0
—
—
—
7.0
—
1.5
0.5
7.5
—
3.0
—
—
—
7.5
—
1.5
0.5
8.5
—
3.0
—
—
—
8.5
—
ns
ns
ns
ns
ns
Flow
Through
Clock to Output in Low-Z
tLZ
1
tS
tH
tKH
tKL
3.0
—
3.0
—
3.0
—
3.0
—
3.0
—
3.0
—
ns
Setup time
Hold time
Clock HIGH Time
Clock LOW Time
Clock to Output in
High-Z
G to Output Valid
1.5
0.5
1.3
1.5
—
—
—
—
1.5
0.5
1.3
1.5
—
—
—
—
1.5
0.5
1.3
1.5
—
—
—
—
1.5
0.5
1.3
1.5
—
—
—
—
1.5
0.5
1.5
1.7
—
—
—
—
1.5
0.5
1.7
2
—
—
—
—
ns
ns
ns
ns
tHZ
1
1.5
2.3
1.5
2.5
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
ns
tOE
—
2.3
—
2.5
—
3.2
—
3.5
—
3.8
—
4.0
ns
G to output in Low-Z
tOLZ
1
0
—
0
—
0
—
0
—
0
—
0
—
ns
G to output in High-Z
tOHZ
1
—
2.3
—
2.5
—
3.0
—
3.0
—
3.0
—
3.0
ns
ZZ setup time
tZZS
2
5
—
5
—
5
—
5
—
5
—
5
—
ns
ZZ hold time
tZZH
2
tZZR
1
—
1
—
1
—
1
—
1
—
1
—
ns
ZZ recovery
20
—
20
—
20
—
20
—
20
—
20
—
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS8161E18D-225I | Quad 2-input Exclusive-OR gates 14-SOIC 0 to 70 |
| GS8161E18D-250 | Quad 2-input Exclusive-OR gates 14-SOIC 0 to 70 |
| GS8161E18D-250I | Quad 2-input Exclusive-OR gates 14-SOIC 0 to 70 |
| GS8161E18T-133 | Quad 2-input Exclusive-OR gates 14-SOIC 0 to 70 |
| GS8161E36D-225I | 25-Bit Configurable Registered Buffer With Address-Parity Test 96-LFBGA 0 to 70 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS8161E18D-225I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs |
| GS8161E18D-250 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs |
| GS8161E18D-250I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:1M x 18, 512K x 32, 512K x 36 18Mb Sync Burst SRAMs |
| GS8161E18DD-150 | 制造商:GSI Technology 功能描述:165 BGA - Bulk |
| GS8161E18DD-200 | 制造商:GSI Technology 功能描述:165 BGA - Bulk |
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