參數(shù)資料
型號(hào): GS8160F18
廠商: GSI TECHNOLOGY
英文描述: 16Mb(1M x 18Bit)Sync Burst SRAM(16M位(1M x 18位)同步靜態(tài)RAM(帶2位脈沖地址計(jì)數(shù)器))
中文描述: 16Mb的(100萬(wàn)x 18位)同步突發(fā)靜態(tài)存儲(chǔ)器(1,600位(100萬(wàn)× 18位)同步靜態(tài)隨機(jī)存儲(chǔ)器(帶2位脈沖地址計(jì)數(shù)器))
文件頁(yè)數(shù): 7/23頁(yè)
文件大?。?/td> 457K
代理商: GS8160F18
Rev: 2.06 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
7/23
1999, Giga Semiconductor, Inc.
Preliminary
GS8160F18/32/36T-7/8/8.5/10/11
Mode Pin Functions
Note:
There is a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as
specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
BPR 1999.05.18
Byte Write Truth Table
Notes:
1.
2.
3.
4.
All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.
Byte Write Enable inputs B
A
, B
B
, B
C
, and/or B
D
may be used in any combination with BW to write single or multiple bytes.
All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.
Bytes “
C
” and “
D
” are only available on the x32 and x36 versions.
Mode Name
Pin
Name
State
Function
Burst Order Control
LBO
L
H
Linear Burst
Interleaved Burst
Active
Standby, I
DD
= I
SB
Power Down Control
ZZ
L or NC
H
Function
GW
BW
B
A
B
B
B
C
B
D
Notes
Read
H
H
X
X
X
X
1
Read
H
L
H
H
H
H
1
Write byte a
H
L
L
H
H
H
2, 3
Write byte b
H
L
H
L
H
H
2, 3
Write byte c
H
L
H
H
L
H
2, 3, 4
Write byte d
H
L
H
H
H
L
2, 3, 4
Write all bytes
H
L
L
L
L
L
2, 3, 4
Write all bytes
L
X
X
X
X
X
Note: The burst counter wraps to initial state on the 5th clock.
I
nterleaved Burst Sequence
Note: The burst counter wraps to initial state on the 5th clock.
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11
00
01
10
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00
01
10
11
2nd address
01
00
11
10
3rd address
10
11
00
01
4th address
11
10
01
00
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