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參數(shù)資料
| 型號(hào)： | GS8150F36 |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 16Mb（512K x 36Bit）Synchronous Burst SRAM(16M位（512K x 36位）同步靜態(tài)RAM（帶2位脈沖地址計(jì)數(shù)器）) |
| 中文描述： | 16Mb的（為512k × 36Bit）同步突發(fā)靜態(tài)存儲(chǔ)器（1,600位（為512k × 36位）同步靜態(tài)隨機(jī)存儲(chǔ)器（帶2位脈沖地址計(jì)數(shù)器）） |
| 文件頁數(shù)： | 9/23頁 |
| 文件大?。?/td> | 456K |
| 代理商： | GS8150F36 |
Rev: 1.01 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
9/23
2000, Giga Semiconductor, Inc.
Preliminary
GS8150F18/32/36T-7/8/8.5/10/11
Simplified State Diagram
First Write
First Read
Burst Write
Burst Read
Deselect
R
W
CR
CW
X
X
W
R
R
W
R
X
X
X
S
S
CR
R
CW
CR
CR
Notes:
1.
2.
The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
The upper portion of the diagram assumes active use of only the Enable (E1, E2, and E3) and Write (B
A
, B
B
, B
C
, B
D
, BW, and GW)
control inputs and that ADSP is tied high and ADSC is tied low.
The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and
assumes ADSP is tied high and ADV is tied low.
3.
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