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參數(shù)資料
| 型號： | GS7660 |
| 廠商： | Vishay Intertechnology,Inc. |
| 英文描述： | Switched-Capacitor Voltage Converter |
| 中文描述： | 開關(guān)電容電壓轉(zhuǎn)換器 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大小： | 112K |
| 代理商： | GS7660 |
GS7660
Vishay
formerly General Semiconductor
www.vishay.com
6
Document Number 74819
24-May-02
To better understand the theory of operation, a review of
the basic switched capacitor building block is helpful (see
Fig. 8). Referring to Fig. 8 and looking at one full cycle of
operation, the charge being drained by the load is Qavg or
IL x T (T being the time period of one full cycle).
All the charge (
q) flowing into the output is being delivered
by the input to C1 during only half the cycle. Under steady-
state condition, C1 will charge to the level of the input voltage
(V
IN
) and discharge to the peak level of the output voltage
(V
OUT
).Therefor the voltage change on C1 is V
IN
–
V
OUT
.
Where f is one-half the oscillator frequency.This resistance
is a major component of the output resistance of switched
capacitor circuits.
With C1 = C2 = 10
μ
F and Fosc = 10kHz, this resistance
represents 20
.
Under the same conditions, the typical value in the
“
Electrical Characteristics
”
section of the GS7660 is 35
.
V
IN
C1
f
C2
R
LOAD
V
OUT
Fig. 8
–
Switched Capacitor Model
Q
avg
=
q = C1(V
in
–
V
out
)
I
L
x T = C1(V
in
–
V
out
) or I
L
= f
x C1(V
in
–
V
out
) f = 1/T
(V
in
–
V
out
)
1
f x C1
I
L
=
and R
EQUIV
=
(See fig. 9)
1
f x C1
Design Information
Low Voltage (L
V
) Pin
Fig. 10 (below) shows a simplified circuit diagram of the
GS7660.
It shows a voltage regulator between the V
IN
and Gnd, in
series with the Oscillator.
Grounding the LV pin removes the regulator from this
series path and improves low voltage performance down to
1.5V. For supply voltages less than 3.0V, the LV pin should
be connected to ground and left open for voltages above
3.0V.
The LV pin can be left grounded over the total range of
Input Voltages.This will improve low voltage operation and
increase oscillator frequency. The disadvantage is
increased quiescent current and reduced efficiency at
higher voltages.
1M
BOOST
pin 1
OSC
pin 7
LV
pin 6
GND
pin 3
CAP-
pin 4
S2
S1
S4
S3
CAP+
pin 2
V
IN
pin 8
V
pin 5
÷
2
Q
O
I
R
Q
Fig. 10
–
Functional Diagram
R
EQUIV
=
R
EQUIV
V
OUT
R
LOAD
1
V
IN
f
×
C1
C2
Fig. 9
–
Equivalent Impedance
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