• <var id="unpcr"></var>
  • <li id="unpcr"><meter id="unpcr"><xmp id="unpcr"></xmp></meter></li>
    <thead id="unpcr"><tr id="unpcr"><label id="unpcr"></label></tr></thead>
  • <dl id="unpcr"><thead id="unpcr"><noframes id="unpcr">
    <big id="unpcr"><form id="unpcr"><label id="unpcr"></label></form></big>
  • <thead id="unpcr"><meter id="unpcr"><label id="unpcr"></label></meter></thead>
  • <dfn id="unpcr"><tbody id="unpcr"></tbody></dfn>
            
    
    
    參數(shù)資料
    型號(hào): GS71108ATP-12T
    英文描述: x8 SRAM
    中文描述: x8的SRAM
    文件頁數(shù): 5/15頁
    文件大?。?/td> 240K
    代理商: GS71108ATP-12T
    Rev: 1.02 10/2001
    Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
    5/15
    2001, Giga Semiconductor, Inc.
    GS71108ATP/J/SJ/U
    AC Test Conditions
    AC Characteristics
    * These parameters are sampled and are not 100% tested
    Read Cycle
    Parameter
    Symbol
    -6
    -8
    -10
    -12
    Unit
    Min
    Max
    Min
    Max
    Min
    Max
    Min
    Max
    Read cycle time
    t
    RC
    6
    8
    10
    12
    ns
    Address access time
    t
    AA
    6
    8
    10
    12
    ns
    Chip enable access time (CE)
    t
    AC
    6
    8
    10
    12
    ns
    Output enable to output valid (OE)
    t
    OE
    3.0
    3.5
    4
    5
    ns
    Output hold from address change
    t
    OH
    3
    3
    3
    3
    ns
    Chip enable to output in low Z (CE)
    t
    LZ
    *
    3
    3
    3
    3
    ns
    Output enable to output in low Z (OE)
    t
    OLZ
    *
    0
    0
    0
    0
    ns
    Chip disable to output in High Z (CE)
    t
    HZ
    *
    3
    4
    5
    6
    ns
    Output disable to output in High Z (OE)
    t
    OHZ
    *
    3.0
    3.5
    4
    5
    ns
    DQ
    VT = 1.4 V
    50
    30pF
    1
    DQ
    3.3 V
    Output Load 1
    Output Load 2
    589
    434
    5pF
    1
    Note:
    1.
    2.
    Include scope and jig capacitance.
    Test conditions as specified with output loading as shown in
    Fig. 1
    unless otherwise noted.
    Output load 2 for t
    LZ
    , t
    HZ
    , t
    OLZ
    and t
    OHZ
    3.
    Parameter
    Conditions
    Input high level
    V
    IH
    = 2.4 V
    Input low level
    V
    IL
    = 0.4 V
    Input rise time
    tr = 1 V/ns
    Input fall time
    tf = 1 V/ns
    Input reference level
    1.4 V
    Output reference level
    1.4 V
    Output load
    Fig. 1& 2
    相關(guān)PDF資料
    PDF描述
    GS71108ATP-8IT x8 SRAM
    GS71108ATP-8T x8 SRAM
    GS71108AU-10IT x8 SRAM
    GS71108AU-10T x8 SRAM
    GS71108AU-12IT x8 SRAM
    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    GS71108ATP-7 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128K x 8 1Mb Asynchronous SRAM
    GS71108ATP-7I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128K x 8 1Mb Asynchronous SRAM
    GS71108ATP-8 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128K x 8 1Mb Asynchronous SRAM
    GS71108ATP-8I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128K x 8 1Mb Asynchronous SRAM
    GS71108ATP-8IT 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM