
GS1535 Data Sheet
18557 - 8
February 2005
16 of 22
The DDI inputs are designed to be DC interfaced with the output of the GS1524
Cable Equalizer. There are on chip 50
termination resistors which come to a
common point at the DDI_VT pins. Connect a 10nF capacitor to this pin and
connect the other end of the capacitor to ground. This end-terminates the
transmission line at the inputs for optimum performance.
If only one input pair is used, connect the unused positive inputs to +3.3V and leave
the unused negative inputs floating. This helps to eliminate crosstalk from potential
noise that would couple to the unused input pair.
3.7 Automatic And Manual Data Rate Selection
The GS1535 can be configured to manually lock to a specific data rate or
automatically search for and lock to the incoming data rate. The AUTO_MAN pin
selects Automatic data rate detection mode (AUTO mode) when HIGH and manual
data rate selection mode (MANUAL mode) when LOW.
In AUTO mode, the SS[2:0] bi-directional pins become outputs and the bit pattern
indicates the data rate that the PLL is locked to (or previously locked to). The
"search algorithm" cycles through the data rates (see
Figure 3-3
) and starts over if
that data rate is not found.
Figure 3-3: Data Rate Search Pattern
NOTE: When the device is in AUTO mode, the SD/
HD
output will toggle when the
reclocker is not locked, (LD=LOW). The logic level of SD/
HD
will depend on the
current state of the search algorithm. If the device is also in bypass mode, and the
SD/
HD
signal is used to set the slew rate of the GS1528 Cable Driver, that slew
rate will change dynamically when the reclocker is not locked.
In MANUAL mode, the SS[2:0] pins become inputs and the data rate can be
programmed. In this mode, the search algorithm is disabled and the GS1535's PLL
will only lock to this data rate.
Table 3-2
shows the bit pattern at SS[2:0] for the data rate selected (in MANUAL
mode) or the data rate that the PLL has locked to (in AUTO mode).
143 Mb\s
177 Mb\s
270Mb\s
360 Mb\s
540 Mb\s
1.485Mb\s
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