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參數(shù)資料
| 型號： | GS1532-CF |
| 廠商： | Gennum Corporation |
| 英文描述： | GS1532 HD-LINX-TM II Multi-Rate Serializer |
| 中文描述： | GS1532的HD - LINX進程，商標第二多速率串行器 |
| 文件頁數(shù)： | 27/52頁 |
| 文件大?。?/td> | 512K |
| 代理商： | GS1532-CF |
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GS1532 Data Sheet
21498 - 6
June 2005
27 of 52
3.3 SMPTE Mode
The GS1532 is said to be in SMPTE mode when the SMPTE_BYPASS pin is set
HIGH and the DVB_ASI pin is set LOW.
In this mode, the parallel data will be scrambled according to SMPTE 259M or
292M, and NRZ-to-NRZI encoded prior to serialization.
3.3.1 Internal Flywheel
The GS1532 has an internal flywheel which is used in the generation of internal /
external timing signals, and in automatic video standards detection. It is
operational in SMPTE mode only.
The flywheel consists of a number of counters and comparators operating at video
pixel and video line rates. These counters maintain information about the total line
length, active line length, total number of lines per field / frame and total active lines
per field / frame for the received video standard.
When DETECT_TRS is LOW, the flywheel will be locked to the externally supplied
H, V, and F timing signals.
When DETECT_TRS is HIGH, the flywheel will be locked to the embedded TRS
signals in the parallel input data. Both 8-bit and 10-bit TRS code words will be
identified by the device.
The flywheel 'learns' the video standard by timing the horizontal and vertical
reference information supplied a the H, V, and F input pins, or contained in the TRS
ID words of the received video data. Full synchronization of the flywheel to the
received video standard therefore requires one complete video frame.
Once synchronization has been achieved, the flywheel will continue to monitor the
received TRS timing or the supplied H, V, and F timing information to maintain
synchronization.
3.3.2 HVF Timing Signal Extraction
As discussed above, the GS1532's internal flywheel may be locked to externally
provided H, V, and F signals when DETECT_TRS is set LOW by the application
layer.
The H signal timing should also be configured via the H_CONFIG bit of the internal
IOPROC_DISABLE register as either active line based blanking or TRS based
blanking, (see
Packet Generation and Insertion on page 32
).
Active line based blanking is enabled when the H_CONFIG bit is set LOW. In this
mode, the H input should be HIGH for the entire horizontal blanking period,
including the EAV and SAV TRS words. This is the default H timing assumed by
the device.
When H_CONFIG is set HIGH, TRS based blanking is enabled. In this case, the H
input should be set HIGH for the entire horizontal blanking period as indicated by
the H bit in the associated TRS words.
相關PDF資料 |
PDF描述 |
|---|---|
| GS1532-CFE3 | GS1532 HD-LINX-TM II Multi-Rate Serializer |
| GS1535-CFU | GS1535 HD-LINX II-TM Multi-Rate SDI Automatic Reclocker |
| GS1535-CFUE3 | GS1535 HD-LINX II-TM Multi-Rate SDI Automatic Reclocker |
| GS1535A | GS1535A / GS9065A HD-LINX-R II Multi-Rate SDI Automatic Reclocker |
| GS1535ACFUE3 | GS1535A / GS9065A HD-LINX-R II Multi-Rate SDI Automatic Reclocker |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| GS1532-CFE3 | 制造商:Gennum Corporation 功能描述:Multi Rate Serializer 80-Pin LQFP |
| GS1535 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GS1535 HD-LINX II-TM Multi-Rate SDI Automatic Reclocker |
| GS1535A | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:Multi-Rate SDI Automatic Reclocker |
| GS1535A_06 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:Multi-Rate SDI Automatic Reclocker |
| GS1535ACFUE3 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:Multi-Rate SDI Automatic Reclocker |
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