參數(shù)資料
型號(hào)： GMS87C2020LQ
廠商： HYNIX SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： MEMORY CARD COMPACTFLASH 128MB
中文描述： 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP64
封裝： LQFP-64
文件頁(yè)數(shù)： 47/107頁(yè)
文件大?。?/td> 1482K
代理商： GMS87C2020LQ
HMS81C2012A/2020A
SEP. 2004 Ver 2.00
43
Watchdog Timer Control
Figure 11-2 shows the watchdog timer control register.
The watchdog timer is automatically disabled after reset.
The CPU malfunction is detected during setting of the de-
tection time, selecting of output, and clearing of the binary
counter. Clearing the binary counter is repeated within the
detection time.
If the malfunction occurs for any cause, the watchdog tim-
er output will become active at the rising overflow from
the binary counters unless the binary counter is cleared. At
this time, when WDTON=1, a reset is generated, which
drives the RESET pin to low to reset the internal hardware.
When WDTON=0, a watchdog timer interrupt (WDTIF) is
generated.
The watchdog timer temporarily stops counting in the
STOP mode, and when the STOP mode is released, it au-
tomatically restarts (continues counting).
Figure 11-2 WDTR: Watchdog Timer Data Register
Example: Sets the watchdog timer detection time to 0.5 sec at 4.19MHz
7
6
5
4
3
2
1
0
Clear count flag
0: Free-run count
1: When the WDTCL is set to "1", binary counter
is cleared to “0”. And the WDTCL becomes “0” automatically
after one machine cycle. Counter count up again.
INITIAL VALUE: 0111_1111
B
ADDRESS: 0ED
H
WDTR
W
W
W
W
7-bit compare data
W
W
W
W
NOTE:
The WDTON bit is in register CKCTLR.
WDTCL
LDM
LDM
CKCTLR,#3FH
WDTR,#04FH
;
Select 1/2048 clock source
,
WDTON
←
1, Clear Counter
LDM
:
:
:
:
LDM
:
:
:
:
LDM
WDTR,#04FH
;
Clear counter
WDTR,#04FH
;
Clear counter
WDTR,#04FH
;
Clear counter
Within WDT
detection time
Within WDT
detection time
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