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參數(shù)資料
| 型號： | GMS81516BT |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | [General Purpose(1) : ADC/ LED/ SCI/ PWM] |
| 中文描述： | [通用（1）：藝術(shù)發(fā)展局/發(fā)光/工商/脈寬調(diào)制] |
| 文件頁數(shù)： | 56/110頁 |
| 文件大?。?/td> | 1980K |
| 代理商： | GMS81516BT |
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GMS81508B/16B/24B, GMS82512/16/24
MAY. 2001 Ver 2.0
53
13.1 Transmission/Receiving Timing
The serial transmission is started by setting SIOST(bit1 of
SIOM) to “1”. After one cycle of SCK, SIOST is cleared
automatically to “0”. The serial output data from 8-bit shift
register is output at falling edge of SCLK. And input data
is latched at rising edge of SCLK pin. When transmission
clock is counted 8 times, serial I/O counter is cleared as
‘0”. Transmission clock is halted in “H” state and serial I/
O interrupt(IFSIO) occurred.
Figure 13-3 Timing Diagram of Serial I/O
13.2 The Serial I/O operation by SRDY pin
Transmission clock = external clock
The SRDY pin becomes “L” by SIOST = “1”. This signal
tells to the external system that this device is ready for se-
rial transmission. The external system detects the “L” sig-
nal and starts transmission. The SRDY pin becomes “H” at
the first rising edge of transmission clock.
Transmission clock = internal clock
The I/O of SRDY pin is input mode. When the external
system is ready for serial transmission, The “L” level is in-
putted at this pin. At this time this device starts serial trans-
mission.
D1
D0
SIOST FLAG
SOUT PIN
Input Clock
SCLK PIN
D4
D3
D2
D7
D6
D5
D1
D0
SIN PIN
D4
D3
D2
D7
D6
D5
SIOIF
INTERRUPT SIGNAL
Output
Latch
SRDY(Output)
SIOST
SRDY(Input)
SIOST
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