參數(shù)資料
型號(hào)： GMS34140T
廠(chǎng)商： Hynix Semiconductor Inc.
英文描述： 4-BIT SINGLE CHIP MICROCOMPUTERS
中文描述： 4位單片機(jī)微機(jī)
文件頁(yè)數(shù)： 26/49頁(yè)
文件大?。?/td> 328K
代理商： GMS34140T
2 - 8
Initial Reset Circuit
RESET pin must be down to "L" more than 4 machine cycle by outside
capacitor or other for power on reset.
The mean of 1 machine cycle is 6/f
OSC
or 48/f
OSC
, however, operating voltage
must be in recommended operating conditions, and clock oscillating stability.
* It is required to adjust C value depending on rising time of power supply.
(Example shows the case of rising time shorter than 10ms.)
1
RESET
0.1uF
Chapter 2. Architecture
Watch Dog Timer (WDT)
Watch dog timer is organized binary of 14 steps. The signal of f
OSC
/6 cycle comes
in the first step of WDT after WDT reset. If this counter was overflowed, reset
signal automatically come out so that internal circuit is initialized.
The overflow time is 6
2
13
/f
OSC
(108.026ms at f
OSC
=455KHz.)
8
6
2
13
/f
OSC
(108.026ms at f
OSC
= 3.64MHz)
Normally, the binary counter must be reset before the overflow by using reset
instruction (WDTR) or / and REMOUT port HIGH(Y-reg=8, So instruction execution).
* It is constantly reset in STOP mode. When STOP is released, counting is
restarted. (Refer to 2-9 STOP function>)
Binary counter
(14 steps)
RESET (edge-trigger)
f
OSC
/6 or f
OSC
/48
CPU reset
Reset
by instruction
REMOUT
output
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