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參數(shù)資料
| 型號(hào)： | GM71S17803C(CL) |
| 英文描述： | 2Mx8|5V|2K|5/6|FP/EDO DRAM - 16M |
| 中文描述： | 2Mx8 | 5V的| 2K | 5 / 6 |計(jì)劃生育/ EDO公司的DRAM - 1,600 |
| 文件頁(yè)數(shù)： | 9/10頁(yè) |
| 文件大?。?/td> | 113K |
| 代理商： | GM71S17803C(CL) |
GM71CS16160CL
GM71C16160C
Rev 0.1 / Apr01
Either
t
R C H
or
t
R R H
must be satisfied for a read cycles.
14.
t
OFF
(max) and
t
OEZ
(max) define the time at which the outputs achieve the open circuit
condition and are not referred to output voltage levels.
,
t
t
are not restrictive operating parameters. They are included in
the data sheet as electrical characteristics only; if
t
cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle
; if
t
R W D
>=
t
R W D
(min),
t
C W D
>=
t
t
A W D
t
t
C PW
contain data read from the selected cell; if neither of the above sets of conditions is satisfied,
the condition of data out (at access time)is indeterminate.
W C S
,
>=
t
W C S
(min), the cycle is an early write
>=
t
A W D
(min), or
t
C W D
t
C W D
t
WE leading edge in delayed write or read-modify-write cycles.
17.
t
R A SP
18. A ccess time is determined by the longest among
A A
t
19. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying
data to the device. A fter RA S is reset, if
t
OE H
>=
t
C W L
, the I/O pin will remain open circuit
(high impedance); if
t
OE H
<
t
C W L
, invalid data will be out at each I/O.
20. When both UCA S and LCA S go low at the same time, all 16-bit data are written into the device.
UCA S and LCA S cannot be staggered within the same write/read cycles.
21. A ll the V
C C
and V
SS
pins shall be supplied with the same voltages.
22.
t
A SC
,
t
C A H
,
t
R C S
,
t
W C S
,
t
W C H
,
t
C SR
and
t
R PC
are determined by the earlier falling edge of UCA S
or LCA S.
23.
t
C R P
,
t
C H R
,
t
R C H
,
t
A C P
and
t
C PW
are determined by the later rising edge of UCA S or LCA S.
24.
t
C W L
,
t
DH
,
t
D S
and
t
C SH
should be satisfied by both UCA S and LCA S.
25.
t
C P
is determined by that time the both UCA S and LCA S are high.
26. When output buffers are enabled once, sustain the low impedance state until valid data is
obtained.
W hen output buffer is turned on and off within a very short time, generally it causes large
V
C C
/V
SS
line noise, which causes to degrade V
IH
min/V
IL
max level.
27. Please do not use
t
R A SS
timing, 10us
<=
t
transition state from normal operation mode to self refresh mode. If
R A SS
>=
100us, then
RA S precharge time should use
t
R PS
instead of
t
RP
.
28. If you use distributed CBR refresh within 15.6us interval in normal read/write cycle, CBR
refresh should be executed within 15.6us immediately after exiting from and before entering
into self refresh mode.
29. If you use RA S only refresh or CBR burst refresh mode in normal read/write cycle, 4096 or
1024 cycles of distributed CBR refresh with 15.6us interval should be executed within 64 or
16ms immediately after exiting from and before entering into the self refresh mode.
30. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from
self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode
again.
31. H or L (H : V
IH
(min)
<=
V
,and
t
A C P
IH
IL
<=
V
IN
<=
V
IL
(max))
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相關(guān)代理商/技術(shù)參數(shù) |
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