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參數(shù)資料
| 型號(hào)： | GM71S17400C(CL) |
| 英文描述： | 4Mx4|5V|2K|5/6/7|FP/EDO DRAM - 16M |
| 中文描述： | 4Mx4 | 5V的| 2K | 5/6/7 |計(jì)劃生育/ EDO公司的DRAM - 1,600 |
| 文件頁(yè)數(shù)： | 3/10頁(yè) |
| 文件大?。?/td> | 113K |
| 代理商： | GM71S17400C(CL) |
GM71CS16160CL
GM71C16160C
Rev 0.1 / Apr’01
T ruth T able
Notes: 1. H : H igh (inactive) L: Low(active) D: H or L
2.
t
W C S
>= 0ns Early write cycle
t
W C S
<= 0ns Delayed write cycle
3. Mode is determined by the OR function of the UCA S and LCA S. (Mode is set by earliest of
UCA S and LCA S active edge and reset by the latest of UCA S and LCA S inactive edge.) H owever
write OPERA TION and output H igh-Z control are done independently by each UCA S,LCA S.
ex) if RA S = H to L , UCA S = H , L CA S = L , then CA S-before-RA S refresh cycle is selected.
L C A S
H
L
L
L
D
H
L
H
D
H
H
L
D
H
H
H
D
D
L
L
Output
Open
V alid
V alid
V alid
Lower byte
Upper byte
Word
Operation
Standby
RA S-only
Refresh cycle
Read cycle
L
L
L
L
L
L
H
L
H
Early write cycle
L
H
L
L
H
Open
Open
Open
L
L
L
L
Undefined
Delayed Write
cycle
L
L
L
H
H
H to L
L
C BR R efresh
or
Self Refresh
(L-series)
H to L
H
L
H to L
L
L
R A S
UC A S
W E
O E
Notes
1,3
1,3
1,3
1,3
1,3
1,2,3
1,2,3
1,3
Lower byte
Upper byte
Word
Lower byte
Upper byte
Word
Lower byte
Upper byte
Word
Undefined
Undefined
Open
Open
Open
Open
Open
V alid
V alid
V alid
Word
Word
Word
Word
Read-modify
-write cycle
Read cycle
(Output disabled)
D
D
H to L
H to L
H to L
L
L
L
L
L
L
L
H
L
L
L
L
H
D
D
L
H
H
H
H
L
D
D
D
D
D
D
L to H
L to H
L to H
L
L
L
L
R ecommended D C Operating Conditions
(T
A
= 0 ~
+
70C)
Symbol
Parameter
Unit
V
C C
V
IH
V
IL
Supply V oltage
Input High V oltage
Input Low V oltage
V
V
V
M ax
5.5
6.0
0.8
T yp
5.0
-
-
M in
4.5
2.4
-1.0
Note: A ll voltage referred to V ss.
T he supply voltage with all V CC pins must be on the same level. The supply voltage with all V SS pins must be
on the same level.
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