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參數(shù)資料
| 型號： | GM71C17803C(CL) |
| 英文描述： | 2Mx8|5V|2K|5/6|FP/EDO DRAM - 16M |
| 中文描述： | 2Mx8 | 5V的| 2K | 5 / 6 |計劃生育/ EDO公司的DRAM - 1,600 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 113K |
| 代理商： | GM71C17803C(CL) |
GM71CS16160CL
GM71C16160C
Rev 0.1 / Apr’01
F ast Page M ode R ead-M odify-W rite Cycle
Symbol
Parameter
Note
M ax
Unit
M in
M ax
M in
t
PR W C
85
-
96
-
ns
t
C PW
60
-
68
-
ns
15,23
Fast Page Mode Read-Modify-Write
Cycle Time
W E Delay Time from C A S Precharge
G M 71C (S )16160
C /C L -6
G M 71C (S )16160
C /C L -7
G M 71C (S )16160
C /C L -5
M ax
M in
76
-
53
-
Self R efresh
M ode
Symbol
Parameter
Note
M ax
Unit
M in
M ax
M in
t
R A SS
100
-
100
-
t
R PS
110
-
130
-
ns
t
C H S
-50
-
-50
-
ns
R A S Precharge Time(Self-Refresh)
CA S H old Time(Self-Refresh)
RA S Pulse W idth(Self-Refresh)
G M 71C S 16160
C L -6
G M 71C S 16160
C L -7
us
M ax
M in
100
-
90
-
-50
-
G M 71C S 16160
C L -5
27
1. A C measurements assume
t
T
= 5ns.
2. A n initial pause of 200us is required after power up followed by a minimum of eight initialization
cycles(any combination of cycles containing RA S-only refresh or CA S-before-RA S refresh).
If the internal refresh counter is used, a minimum of eight CA S-before-RA S refresh cycles are
required.
3. Only row address is indispensable on address A 8, A 9, A 10, A 11.
4. Operation with the t
R C D
(max)limit insures that
t
R A C
(max)can be met,
t
R C D
(max)is specified as a
reference point only; if
t
R C D
>=
t
R A D
(max) +
t
A A
(max) -
t
C A C
(max), then access time is controlled
exclusively by
t
C A C
.
5. Operation with the
t
R A D
(max) limit insures that
t
R A C
(max)can be met,
t
R A D
(max)is specified as a
reference point only; if
t
R A D
is greater than the specified
t
R A D
(max)limit, then access time is
controlled exclusively by
t
A A .
6. Either
t
OD D
or
t
C D D
must be satisfied.
7. Either
t
D Z O
or
t
D Z C
must be satisfied.
8. V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals. A lso,
transition times are measured between V
IH
(min) and V
IL
(max).
9. A ssumes that
t
R C D
<=
t
R C D
(max) and
t
R A D
<=
t
R A D
(max). If
t
R C D
or
t
R A D
is greater than the
maximum recommended value shown in this table,
t
R A C
exceeds the value shown.
10. Measured with a load circuit equivalent to 2 TTL load and 100pF.
11. A ssumes that
t
R C D
>=
t
R C D
(max) and
t
R C D
+
t
C A C
(max)
>=
t
R A D
+
t
A A
(max).
12. A ssumes that
t
R A D
>=
t
R A D
(max) and
t
R C D
+
t
C A C
(max)
<=
t
R A D
+
t
A A
(max).
Notes:
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| GM71C17803CJ-5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EDO Page Mode DRAM |
| GM71C17803CJ-6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EDO Page Mode DRAM |
| GM71C17803CJ-7 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EDO Page Mode DRAM |
| GM71C17803CT-5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EDO Page Mode DRAM |
| GM71C17803CT-6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 EDO Page Mode DRAM |
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