
***
Genesis Microchip Confidential ***
gm5115/25 Preliminary Data Sheet
June 2002
10
C5115-DAT-01H
4. FUNCTIONAL DESCRIPTION
A functional block diagram is illustrated below. Each of the functional units shown is described
in the following sections.
Ultra-Reliable
DVI Rx
MCU
RAM
8051-style
Micro-
controller
Test Pattern
Generator
DVI-Compliant
Input
HDCP
Triple ADC
and PLL
Output
Data
Path
Host
Interface
OSD
RAMs
OSD
Controller
Panel
Timing
Controller
Internal
ROM
External
ROM I/F
Parallel
ROM IF
Serial Host I/F
GPIO
Gamma
Control
Clock
Generation
Crystal
Reference
Zoom /
Shrink /
Filter
Brightness /
Contrast /
Hue / Sat /
RealColor /
Moire
Image
Capture /
Measure-
ment
Analog RGB
Input
NVRAM
Serial I/F
Timing
Control
Signals
Panel Data
Figure 3.
gm5115/25 Functional Block Diagram
4
4
.
.
1
1
C
C
l
l
o
o
c
c
k
k
G
G
e
e
n
n
e
e
r
r
a
a
t
t
i
i
o
o
n
n
The gm5115/25 features three clock inputs. All additional clocks are internal clocks derived from
one or more of these:
1. Crystal Input Clock (TCLK and XTAL). This is the input pair to an internal crystal oscillator
and corresponding logic. A 14.3 MHz TV crystal is recommended. Other crystal frequencies
may be used, but require custom programming. This is illustrated in Figure 4 below.
Alternatively, a single-ended TTL/CMOS clock oscillator can be driven into the TCLK pin
(leave XTAL as N/C in this case). This is illustrated in Figure 7 below. This option is
selected by connecting a 10K
pull-up to ROM_ADDR13 (refer to Table 18). See also Table
14.
2. DVI Differential Input Clock (RC+ and RC-)
3. Host Interface Transfer Clock (HCLK)