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參數資料
| 型號： | GM3110 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | XGA/SXGA LCD Controller |
| 中文描述： | 的XGA / SXGA LCD控制器 |
| 文件頁數： | 25/51頁 |
| 文件大?。?/td> | 1379K |
| 代理商： | GM3110 |
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***
Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
June 2002
18
C5110-DAT-01C
Table 15. ADC Characteristics
Track & Hold Amp Bandwidth
MIN
TYP
290 MHz
MAX
NOTE
Guaranteed by design. Note that the Track &
Hold Amp Bandwidth is programmable. 290
MHz is the maximum setting.
Measured at ADC Output.
Independent of full scale RGB input.
Measured at ADC Output.
162.5 MHz
+/-0.9 LSB Fs = 135 MHz
Guaranteed by test.
Fs =135 MHz
Full Scale Adjust Range at RGB Inputs
Full Scale Adjust Sensitivity
0.55 V
0.90 V
+/- 1 LSB
Zero Scale Adjust Sensitivity
Sampling Frequency (Fs)
Differential Non-Linearity (DNL)
No Missing Codes
Integral Non-Linearity (INL)
Channel to Channel Matching
+/- 1 LSB
+/-0.5 LSB
+/- 1.5 LSB
+/- 0.5 LSB
10 MHz
The gm5110/20 ADC has a built in clamp circuit for AC-coupled inputs. By inserting series
capacitors (about 10 nF), the DC offset of an external video source can be removed. The
clamp pulse position and width are programmable.
4.3.3 Clock Recovery Circuit
The SDDS (Source Direct Digital Synthesis) clock recovery circuit generates the clock used
to sample analog RGB data (IP_CLK or source clock). This circuit is locked to HSYNC of
the incoming video signal.
Patented digital clock synthesis technology makes the gm5110/20 clock circuits resistant to
temperature/voltage drift. Using DDS (Direct Digital Synthesis) technology, the clock
recovery circuit can generate any IP_CLK clock frequency within the range of 10MHz to
165MHz.
Window
Capture
SDDS
ADC
R
G
B
IPCLK
HSYNC
HSYNC
(delayed)
24
Phase
Image Phase
Measurement
Figure 11.
gm5110/20 Clock Recovery
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