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參數(shù)資料
| 型號： | GM2110 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | XGA/SXGA LCD Controller |
| 中文描述： | 的XGA / SXGA LCD控制器 |
| 文件頁數(shù)： | 35/51頁 |
| 文件大?。?/td> | 1379K |
| 代理商： | GM2110 |
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***
Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
June 2002
28
C5110-DAT-01C
free-run mode, the display timing is determined only by the values programmed into
the display window and timing registers.
4.11.2 Programming the Display Timing
Display timing signals provide timing information so the Display Port can be connected to an
external display device. Based on values programmed in registers, the Display Output Port
produces the horizontal sync (DHS), vertical sync (DVS), and data enable (DEN) control
signals. The figure below provides the registers that define the output display timing.
Horizontal values are programmed in single pixel increments relative to the leading edge of
the horizontal sync signal. Vertical values are programmed in line increments relative to the
leading edge of the vertical sync signal.
Display Active Window
Display Background Window
Vertical Blanking (Back Porch)
VSYNC Region
H
H
DV_VS_END
DEN **
DHS
DV_BKGND_START
DV_ACTIVE_START
DV_ACTIVE_LENGTH
D
DV_BKGND_END
D
DH_HS_END
DH_BKGND_START
DH_BKGND_END
DH_TOTAL
DH_ACTIVE_START
DH_ACTIVE_WIDTH
Vertical Blanking (Front Porch)
H
**
DEN is not asserted during vertical blanking
Figure 18.
Display Windows and Timing
The double-wide output only supports an even number of horizontal pixels.
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