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參數資料
| 型號： | GLT5160L16P-10TC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 12 AMP MINIATURE POWER RELAY |
| 中文描述： | 1,600（2 -銀行甲524288字× 16位）同步DRAM |
| 文件頁數： | 13/45頁 |
| 文件大小： | 399K |
| 代理商： | GLT5160L16P-10TC |
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13
G-LINK Technology
DEC. 2003 (Rev.2.4)
Burst Interruption
[Read Interrupted by Read]
The burst read operation can be interrupted by a new read of the
same or the other bank. GLT5160L16 allows random column
access. READ to READ interval is 1 CLK minimum.
[Read Interrupted by Write]
Burst read operation can be interrupted by write of the same or the
other bank. Random column access is allowed. In this case, the DQ
should be controlled adequately by using the DQMU / DQML to
prevent the bus contention. The output is disabled automatically 2
cycles after WRITE assertion.
CLK
Figure 9. READ Interrupted by READ (BL=4, CL=3)
Command
A[9:0]
A[10]
BA
Internal Precharge Start Timing
DQ
0
Qj1
Qj0
Qi0
Qk0
REA
READ
READ
Qk2
Qk1
Ql1
Ql0
REA
Yi
Yk
Yl
Yj
0
0
0
0
0
1
0
Ql2
Ql3
CLK
Command
A[9:0]
A[10]
BA
DQMU,
Figure 10. READ Interrupted by WRITE (BL=4, CL=3)
Q
D
Dj0
Qi0
Dj1
REA
Dj3
Dj2
WRITE
Yi
Yj
0
0
0
0
DQM U/ DQML control
Write control
相關PDF資料 |
PDF描述 |
|---|---|
| GLT5160L16P-6FJ | 16M (2-Bank x 524288-Word x 16-Bit) Synchronous DRAM |
| GLT5160L16P-6TC | 16M (2-Bank x 524288-Word x 16-Bit) Synchronous DRAM |
| GLT5160L16P-7FJ | 16M (2-Bank x 524288-Word x 16-Bit) Synchronous DRAM |
| GLT5160L16P-7TC | 12 AMP MINIATURE POWER RELAY |
| GLT5160L16P-8FJ | 16M (2-Bank x 524288-Word x 16-Bit) Synchronous DRAM |
相關代理商/技術參數 |
參數描述 |
|---|---|
| GLT5160L16P-6FJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16M (2-Bank x 524288-Word x 16-Bit) Synchronous DRAM |
| GLT5160L16P-6TC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16M (2-Bank x 524288-Word x 16-Bit) Synchronous DRAM |
| GLT5160L16P-7FJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16M (2-Bank x 524288-Word x 16-Bit) Synchronous DRAM |
| GLT5160L16P-7TC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16M (2-Bank x 524288-Word x 16-Bit) Synchronous DRAM |
| GLT5160L16P-8FJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16M (2-Bank x 524288-Word x 16-Bit) Synchronous DRAM |