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參數(shù)資料
| 型號： | GLT41316-20TQ |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE |
| 中文描述： | 64K的× 16的CMOS動(dòng)態(tài)RAM的快速頁面模式 |
| 文件頁數(shù)： | 8/22頁 |
| 文件大?。?/td> | 1497K |
| 代理商： | GLT41316-20TQ |
G-LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 8 -
Notes
1.
An initial pause of 100
μ
s is required after power-up followed by any 8
RAS
only Refresh or
CAS
before
RAS
Refresh cycles to initialize the internal circuit.
2.
V
IH(min.)
and V
IL(min.)
are reference levels for measuring timing of input signals. Transition times
are measured between V
IH(min.)
and V
IL(max.)
, AC measurements assume t
T
= 3ns.
3
. Measured with an equivalent to 2 TTL loads and 100pF.
4.
For read cycles, the access time is defined as follows:
Input Conditions
Access Time
t
RAD
≤
t
RAD(MAX.)
and t
RCD
≤
t
RCD(MAX.)
t
RAC(MAX.)
t
RAD(max.)
< t
RAD
and t
RCD
≤
t
RCD(MAX.)
t
AA(MAX.)
t
RCD(max.)
< t
RCD
t
CAC(MAX.)
t
RAD(MAX.)
and t
RCD(MAX.)
indicate the points which the access time changes and are not the limits of
operation.
5.
t
WCS
, t
RWD
, t
CWD
and t
AWD
are non restrictive operating parameters. They are included in the data
sheet
as electric characteristics only. If t
WCS
≥
t
WCS(min.)
, the cycle is an early write cycle and the data output
will remain high impedance for the duration of the cycle. If t
CWD
≥
t
CWD(min.)
,t
RWD
≥
t
RWD
(min.)
and
t
AWD
≥
t
AWD(min.)
, then the cycle is a read-modify-write cycle and the data output will contain the data
read from the selected address. If neither of the above conditions is satisfied, the condition of the
data
out is indeterminate.
6.
t
AR
, t
WCR
, and t
DHR
are referenced to t
RAD(max.)
.
7.
t
OFF(max.)
and t
OEZ(max.)
define the time at which the output achieves the open circuit condition and are
not referenced to V
OH
or V
OL
.
8.
t
CRP(min)
requirement should be applicable for
RAS
,
CAS
cycle preceded by any cycles.
9.
Either t
RCH(min.)
or t
RRH(min.)
must be satisfied for a read cycle.
10.
t
WP(min.)
is applicable for late write cycle or read modify write cycle. In early write cycles, t
WCH(min.)
should be satisfied.
11.
This specification is referenced to
CAS
falling edge in early write cycles and to
WE
falling edge in
late write or read modify write cycles.
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| GLT41316-20TS | 3.0V 50ppm/Degrees C, 50uA in SOT23-3 Series (Bandgap) Voltage Reference 3-SOT-23 -40 to 125 |
| GLT41316-30FA | 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE |
| GLT41316-30FB | 3.0V 50ppm/Degrees C, 50uA in SOT23-3 Series (Bandgap) Voltage Reference 3-SOT-23 -40 to 125 |
| GLT41316-30FC | 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE |
| GLT41316-30J3 | 3.3V 50ppm/Degrees C, 50uA in SOT23-3 Series (Bandgap) Voltage Reference 3-SOT-23 -40 to 125 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GLT41316-20TS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE |
| GLT41316-30FA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE |
| GLT41316-30FB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE |
| GLT41316-30FC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE |
| GLT41316-30J3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE |
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