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參數(shù)資料
| 型號： | GL861 |
| 廠商： | Genesys Logic, Inc. |
| 英文描述： | USB 2.0 Controller for PC-DTV Application |
| 中文描述： | USB 2.0控制器適用于PC，數(shù)字電視應(yīng)用 |
| 文件頁數(shù)： | 12/19頁 |
| 文件大小： | 425K |
| 代理商： | GL861 |
GL861 USB 2.0 Controller for PC-DTV
2000-2005 Genesys Logic Inc. - All rights reserved.
Page 12
3.3 Pin Descriptions
Table 3.3 - 100-Pin QFP Pin Descriptions
Pin Name
Pin#
Type
Description
DVDDO
DVDD
DTV_DAT0~7
83~86,2~5
77
P
P
I
1.8V output
1.8V core power
MPEG2-TS data bit 0~7
Read strobe of ICE /Output enable for flash memory. Low
active
Write strobe of ICE /Write enable for flash memory. Low
active.
27,39,81
FSH_OEB
6
I
FSH_WEB
7
I
FSH_ADR0~15
8,9,14~17,
37,
38,71~74,
93~96
I/O
Port 0 and Port 2 for ICE mode/ Address of flash
memory
GPIO0~14
10~13,57~62,
87,88,31,32,34
I/O
(pu: GPIO0, 1,
7, 8, 12, 13, 14
pd: GPIO3, 10)
15 GPIOs
DTV_ERR
21
I
Error indication for MPEG2-TS stream
GND
26,40,41,42,
46,47,56,78,
82,99
P
Ground
HRST_
30
I
(pu)
I
P
I/O
I/O
A
I
O
I/O
I/O
I
I
(pd)
I/O
I/O
I/O
I/O
I
I
P
Hardware reset, low active
EXTCPU
AVDD33
DM
DP
RREF
X1
X2
FSH_DAT4
FSH_DAT5~7
DTV_CLK
33
Use external CPU mode for ICE development.
3.3V analog power
USB D-
USB D+
Reference R
12M crystal in
12M crystal out
Data bus of flash memory/ ALE signal of ICE
Data bus of flash memory
MPEG clock input from demodulator
43,49,50
44
45
48
54
55
63
64,67,68
75
TEST
76
Test mode
FSH_DAT0
89
90
91
92
97
98
Data bus of flash memory/ Clock output for ICE
Data bus of flash memory/ RST pin for ICE mode
Data bus of flash memory/ Interrupt 0 of ICE mode
Data bus of flash memory/ Interrupt 1 of ICE mode
MPEG data valid from demodulator
MPEG packet start from demodulator
3.3V power
FSH_DAT1
FSH_DAT2
FSH_DAT3
DTV_DP
DTV_STR
DVDD33
53,79,100
1,18~20,22~25,
28,29,35,36,51
,52,
65,66,69,70
,80
NC
-
No connection
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