參數(shù)資料
型號(hào)： GL860A-MNGXX
廠商： Genesys Logic, Inc.
英文描述： USB 2.0 UVC Camera Controller
中文描述： 紫外線相機(jī)的USB 2.0控制器
文件頁(yè)數(shù)： 25/42頁(yè)
文件大?。?/td> 1020K
代理商： GL860A-MNGXX
GL860A USB 2.0 UVC Camera Controller
2007 GenesysLogic, Inc. - All rights reserved.
Page 25
Offset 52h – FF3BUF ………………………………………………..………… Default value = 8’h00
FF3DAT7
FF3DAT6
FF3DAT5
FF3DAT4
FF3DAT3
FF3DAT2
FF3DAT1
FF3DAT0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7-0 FF3DAT[7:0]
Data entry for endpoint 3 FIFO.
Writing this register will push data into endpoint 3 TXFIFO, and reading will
pop data from endpoint 3 RXFIFO.
Offset 53h – EP12CTL1 ……………………………………………..………… Default value = 8’h00
--
--
--
--
--
TXASEL2 TXASEL1 TXASEL0
--
--
--
--
--
R/W
R/W
R/W
7-3 RESERVED
-
2-0 TXASEL[2:0]
001 TXAFFSEL1 set 1
010 TXAFFSEL2 set 1
011 TXAFFSEL3 set 1
100 TXAFFSEL4 set 1
101 TXAFFSEL5 set 1
110 TXAFFSEL0 set 1
In normal operation, bulk FIFO is pushed/popped by DTV/SEN engine or USB SIE engine.
But use the register, we can push/pop bulk FIFO by uC.
uC accessing ISO/Bulk IN FIFO:
Set TXFFPSH=1, and use TXAFFSEL to select DATA A FIFO, or use TXBFFSEL to select DATA
B FIFO. Then write data to FF1BUF to begin pushing FIFO.
To pop data from FIFO, just set TXFFPSH = 0, set TXBFFSEL or TXAFFSEL to select DATA
A/DATA B FIFO, and read data from FF1BUF to begin popping FIFO.
After pop/push is complete, uC must clear all FIFO select and control setting on FFCTL.
Offset 54h – EP12CTL2 …….…………………………………………..……… Default value = 8’h00
--
--
DTXEN
TXFMOD TXFFRST RXFFRST TXFFPSH RXFFPSH
--
--
R/W
R/W
R/W
R/W
R/W
R/W
7-6 RESERVED -
5 DTXEN
Firmware set ENDP1 TX mode.
4 TXFMOD
Firmware test EP1 FIFO, read/write byte mode.
3 TXFFRST
Reset TXFIFO, cleared by hardware itself.
2 RXFFRST
Reset RXFIFO, cleared by hardware itself.
1 TXFFPSH
Push indication for TX FIFO
0 RXFFPSH
Push indication for RX FIFO
Offset 55h – EP12CTL2 …….…………………………………………..……… Default value = 8’h00
ANK1_EN
--
--
--
--
ANAKEP2
EP2NAK
EP1NAK
R/W
--
--
--
--
R/W
R/W
R/W
7 ANK1_EN
Force NAK of endpoint 1.
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