參數資料
型號: GL850G-MNGXX
廠商: Genesys Logic, Inc.
英文描述: USB 2.0 HUB Controller
中文描述: USB 2.0集線器控制器
文件頁數: 11/25頁
文件大?。?/td> 330K
代理商: GL850G-MNGXX
GL850G USB 2.0 Low-Power HUB Controller
2000-2007 Genesys Logic Inc. - All rights reserved.
Page 11
HUB Interface
GL850G
Pin Name
48Pin#
I/O Type
Description
OVCUR1~4#
42,40,
30,28
43,41,
31,29
I_5V
(pu)
Active low. Over current indicator for DSPORT1~4
OVCUR1# is the only over current flag for GANG mode.
Active low. Power enable output for DSPORT1~4
PWREN1# is the only power-enable output for GANG mode.
Green LED indicator for DSPORT1~4
*GREEN[1~2] are also used to access the external EEPROM
For detailed information, please refer to Chapter 5.
Amber LED indicator for DSPORT1~4
*Amber[1~2] are also used to access the external EEPROM
For detailed information, please refer to Chapter 5.
0: GL850G is bus-powered.
1: GL850G is self-powered.
This pin is default put in input mode after power-on reset.
Individual/gang mode is strapped during this period. After the
strapping period, this pin will be set to output mode, and then
output high for normal mode.
When GL850G is suspended, this pin will output low.
*For detailed explanation, please see Chapter 5
Gang input:1, output: 0@normal, 1@suspend
Individual input:0, output: 1@normal, 0@suspend
PWREN1~4#
O
PGREEN1~4
45,35,
32,23
1,3,4:O
2:B
(pd)
PAMBER1~4
46,36,
33,24
O
(pd)
PSELF
37
I_5V
PGANG
39
B
Clock and Reset Interface
GL850G
Pin Name
48Pin#
I/O Type
Description
X1
14
I
12MHz crystal clock input.
X2
15
O
12MHz crystal clock output.
Active low. External reset input, default pull high 10K
.
When RESET# = low, whole chip is reset to the initial state.
RESET#
26
I_5V
System Interface
GL850G
Pin Name
48Pin#
I/O Type
Description
TEST
27
I
(pd)
0: Normal operation.
1: Chip will be put in test mode.
Power / Ground
GL850G
Pin Name
48Pin#
I/O Type
Description
AVDD
1,7,12,
16,19
P
3.3V analog power input for analog circuits.
AGND
2,8,13,
20
P
Analog ground input for analog circuits.
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