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參數(shù)資料
| 型號： | GL824-MZGXX |
| 廠商： | Genesys Logic, Inc. |
| 英文描述： | USB 2.0 On-The-Go Controller |
| 中文描述： | 個USB 2.0和On - The - Go控制器 |
| 文件頁數(shù)： | 41/56頁 |
| 文件大?。?/td> | 1464K |
| 代理商： | GL824-MZGXX |
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GL824/GL824C USB 2.0 On-The-Go Controller
2000-2006 Genesys Logic Inc. - All rights reserved.
Page 41
6.5.10 Register Transfers
Figure 6.12
–
Register Transfers Timing
Notes:
1. Device address consists of signals CS0_, CS1_ and DA(2:0).
2. Data consists of IODD(7:0).
3. The negation of IORDY by the device is used to extend the register transfer cycle. The determination of
whether the cycle is to be extended is made by the host after t
A
from the assertion of DIOR_ or DIOW_.
The assertion and negation of IORDY are described as following:
3.1
Device never negates IORDY, devices keeps IORDY released: no wait is generated.
3.2
Device negates IORDY before t
A
, but causes IORDY to be asserted before t
A
. IORDY is released
prior to negation and may be asserted for no more than 5 ns before release: no wait generated.
3.3
Device negates IORDY before t
A
, IORDY is released prior to negation and may be asserted for no
more than 5 ns before release: wait generated. The cycle completes after IORDY is released. For
cycles where a wait is generated and DIOR_ is asserted, the device shall read data on IODD(0:7) for
t
RD
before asserting IORDY.
4.
DMACK_ shall remain negated during a register transfer.
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| GL826 | 制造商:GENESYS 制造商全稱:GENESYS 功能描述:USB 2.0 Multi-Slot Flash Card Reader Controller (All-in-one with Dual SD/MMC bus Interface) |
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