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參數(shù)資料
| 型號： | GL811E |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | USB 2.0 to ATA / ATAPI Bridge Controller |
| 中文描述： | USB 2.0至的ATA / ATAPI控制器橋 |
| 文件頁數(shù)： | 23/35頁 |
| 文件大?。?/td> | 1290K |
| 代理商： | GL811E |
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GL811E USB 2.0 to ATA/ATAPI Bridge Controller
2000-2004 Genesys Logic Inc. - All rights reserved.
Page 23
6.4.3 Ultra DMA data transfer
Table 6.7 - Ultra DMA data burst timing requirements
Mode 0
(in ns)
Mode 1
(in ns)
Mode 2
(in ns)
Mode 3
(in ns)
Mode 4
(in ns)
Name
min
max
min
max
min
max
min
max
Min
max
Comment
t
2CYCTYP
240
160
120
90
60
Typical sustained average
two cycle time
Cycle time allowing for
asymmetry and clock
variations
Two cycle time allowing
for clock variations
Data setup time at
recipient
Data hold time at recipient
Data valid setup time at
sender
Data valid hold time at
sender
First STORBE time
t
CYC
112
73
54
39
25
t
2CYC
230
154
115
86
57
t
DS
15
10
7
7
5
t
DH
5
5
5
5
5
t
DVS
70
48
30
20
6
t
DVH
6
6
6
6
6
t
FS
0
230
0
200
0
170
0
130
0
120
t
LI
0
150
0
150
0
150
0
100
0
100
Limited interlock time
Interlock time with
minimum
Unlimited interlock time
Maximum time allowed
for output drivers to
release
Minimum delay time
required for output
Drivers to assert or negate
t
MLI
20
20
20
20
20
t
UI
0
0
0
0
0
t
AZ
10
10
10
10
10
t
ZAH
20
20
20
20
20
t
ZAD
0
0
0
0
0
t
ENV
20
70
20
70
20
70
20
55
20
55
Envelope time
STROBE to DMARDY_
time
Ready to final STROBE
time
Minimum time to assert
STOP or negate DMARQ
Maximum time before
releasing IORDY
Minimum time before
driving STROBE
Setup and hold times for
DMACK_
Time from STROBE edge
to negation of DMARQ or
assertion of STOP
t
SR
50
30
20
NA
NA
t
RFS
75
70
60
60
60
t
RP
160
125
100
100
100
t
IORDYZ
20
20
20
20
20
t
ZIORDY
0
0
0
0
0
t
ACK
20
20
20
20
20
t
SS
50
50
50
50
50
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