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參數(shù)資料
| 型號： | GL651USB |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 2-PORT USB KEYBOARD HUB CONTROLLER |
| 中文描述： | 2端口USB鍵盤的集線器控制器 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 156K |
| 代理商： | GL651USB |
10 03/06/00
GL651USB USB KEYBOARD HUB CONTROLLER
Version 1.0
with a NAK. EP0OE will be automatically cleared after a successful transmission, or when
endpoint 0 has incidentally accepted another SETUP or OUT transaction.
TXCTL0_KB
( offset 06, default = 00h )
R/W
R/W
R/W
--
EP0STL
EP0OE
EP0SEQ
TXCTL0 of hub. Definition of each bit is the same as TXCTL0_HB.
TXCTL123
( offset 07, default = 00h )
R/W
R/W
R/W
--
EPnSTL
EPnOE
EPnSEQ
Endpoint n(1~3) transmit setting –
EPnCNT3~0
: number of data bytes to transmit.
EPnOE
: enable data transmit
1 – ready to transmit data packet
0 – not ready to transmit data packet (default)
EPnSEQ
: data packet type
0 –DATA0
1 –DATA1
EPnSTL
: set endpoint n stall
1 – EPn will respond to USB host controller with STALL packet
0 – default
After preparing the data to transmit, the micro-controller should setup this register to enable
endpoint n data transmit. If EPnOE = 0, endpoint n will respond to a valid IN transaction with a
NAK. After a successful transmission, the device will automatically clear EPnOE. EPSEL1~3
must be set before settingTXCTL123.
FFDAT0_HB
( offset 08, default = 00h )
R/W
R/W
R/W
R/W
FFD7
FFD6
FFD5
FFD4
FFDAT0 of hub.
Each FFDAT0 read/write will automatically increase the FIFO pointer, which is a 3-bit circular
counter, by 1. Writing FPRST0 with ‘1’ (in BUFCTL) will reset the pointer. Note that to fill
FFDAT0, RXDIS (in RXCTL0) must be first cleared.
FFDAT0_KB
( offset 09, default = 00h )
R/W
R/W
R/W
R/W
FFD7
FFD6
FFD5
FFD4
FFDAT0 of hub. Definition of each bit is the same as FFDAT0_HB.
FFDAT123
( offset 0A, default = 00h )
R/W
R/W
R/W
R/W
FFD7
FFD6
FFD5
FFD4
Each FFDAT123 read/write will automatically increase the FIFO pointer, which is a 3-bit
circular counter, by 1. Writing FPRST1 with ‘1’ (in BUFCTL) will reset the pointer. EPSEL1~3
must be set before setting FFDAT123.
BUFCTL
( offset 0B)
--
--
--
--
Data buffer control –
FPRST[1:0]
: Reset FIFO pointer of FIFO 0~3.
R/W
R/W
R/W
R/W
EP0CNT3
EP0CNT2
EP0CNT1
EP0CNT0
R/W
R/W
R/W
R/W
EPnCNT3
EPnCNT2
EpnCNT1
EpnCNT0
R/W
FFD3
R/W
FFD2
R/W
FFD1
R/W
FFD0
R/W
FFD3
R/W
FFD2
R/W
FFD1
R/W
FFD0
R/W
FFD3
R/W
FFD2
R/W
FFD1
R/W
FFD0
R/W
FPRST1
R/W
FPRST0
--
--
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