Revision 1.3
Mar.22 2001
-9-
GL646USB
H_BUSY(DMA_ACK)
O
EPP nWait or DMA Acknowledge
H_ACK(IO_RD)
O
EPP Intr or DMA IO Read
H_PE(IO_WR)
O
EPP AckDataReq or DMA IO Write
H_ERR(DMA_DRQ)
B
EPP nDataAvail or DMA Data Request
HD0~HD7
B
EPP Data Bus or MPU Data Bus
DMAD0~7
B
DMA Data Bus
Support IO Ports
GPIO1~12
B
General Purpose Input Output
MT_PH0~5
O
Bi-polar : MT_PH5=PHASE1
MT_PH4=PHASE2
MT_PH3=I11
MT_PH2=I01
MT_PH1=I12
MT_PH0=I02
Uni-polar : MT_PH3=PHASE A
MT_PH2=PHASE B
MT_PH1=PHASE /A
MT_PH0=PHASE /B
HOME
I
Sense carriage home position
USB Interface
VMO
B
D+
VPO
B
D-
VCP
P
3.3V
CCD/CIS Control Signals
CCD_CK1X
O
CCD Shift register clock1 or CIS clock output
CCD_CK2X
O
CCD Shift register clock2 or CIS clock output
CCD_CPX
O
CCD Clamp gate clock or CIS clock output
CCD_RSX
O
CCD Reset gate clock or CIS clock output
CCD_TGX
O
CCD Transfer gate clock for R channel or CIS Line start pulse
CCD_TGG
O
CCD Transfer gate clock for G channel
CCD_TGB
O
CCD Transfer gate clock for B channel
RGBSEL0
O
RGB channel selection pin or CCD Shift register clock3
XPA_SW
O
Transparency lamp power control or CIS Green LED array control
LAMP_SW
O
Flatbed lamp power control or CIS Red LED array control
LED_B
O
CIS Blue LED array control
FRONT-END
R_IN
AI
Red channel input signal
G_IN
AI
Green channel input signal
B_IN
AI
Blue channel input signal
VRLC
AO
Selectable analog output voltage for RLC
VMID
AO
ADC reference voltage. Derived from VRU. Normally is 2.5V
VRT
AO
ADC reference voltage. Derived from VRU. Normally is 3.3V
VRB
AO
ADC reference voltage. Derived from VRU. Normally is 1.7V
VRU
AI
ADC reference voltage. Normally connected to 5V analog supply
OP0~OP7
O
ADC digital data output
VSMP(CDSCLK2)
O
Wolfson type : Video sample synchronization pulse.