參數(shù)資料
型號: GL600USB-B
廠商: Electronic Theatre Controls, Inc.
英文描述: USB MOUSE MICROCONTROLLER
中文描述: USB鼠標單片機
文件頁數(shù): 13/38頁
文件大?。?/td> 352K
代理商: GL600USB-B
13
06/19/2000
GL600USB/GL600USB-A/GL600USB-B
Revision 1.3
Value on POR: “- - - 0 0 0 0 0”
Note 1: “R/W1C” means read-only and write “1” to clear bit
DEVADR (Address 13h, USB device address register)
R/W
DADR6
DADR5
Write this register to set the USB device address
Value on POR: “- 0 0 0 0 0 0 0”
FFCNT0 (Address 14h, Byte count buffer for endpoint 0)
R/O
[1]
R/O
RXCNT3
RXCNT2
RXCNT1
RXCNT[3:0]: Number of bytes received by endpoint 0 OUT transaction
TXCNT[3:0]: Number of bytes to be sent by endpoint 0 IN transaction
Value on POR: “x x x x x x x x”
Note 1: “R/O” means read-only bit. Writing this bit is no effect.
FFCNT1 (Address 15h, Byte count buffer for endpoint 1)
TXCNT[3:0]: Number of bytes to be sent by endpoint 1 IN transaction
Value on POR: “- - - - x x x x”
FFCTL (Address 16h, FIFO control register)
W/O
[1]
R/W
FFRST1
TXSEQ1
FFRST1: Reset endpoint 1 FIFO read/write pointer
Write “1” to this bit will reset endpoint 1 FIFO read/write pointer. Data in endpoint 1 FIFO remain
unchanged. Before data are written into endpoint 1 FIFO, FFRST1 should be written first.
TXSEQ1: Endpoint 1 transmitting data sequence bit
1: Transmitting data use DATA1 as PID
0: Transmitting data use DATA0 as PID
TXOE1: Endpoint 1 FIFO data ready bit
1: Endpoint 1 FIFO data are ready to be transmitted. Data will be transmitted when a valid IN
token is received. This bit is automatically cleared by hardware after the transaction complete
(ACK is received).
0: Endpoint 1 FIFO data are not ready to be transmitted. Endpoint 1 will respond with a NAK to a
valid IN transaction.
RXDIS0: Endpoint 0 receiving not available bit
1: Endpoint 0 FIFO is not available. The received data cannot be pushed into FIFO. The USB
controller will respond with a NAK to a valid OUT transaction. This bit is set by hardware when
endpoint 0 data is received (both SETUP and OUT transaction) and should be cleared by firmware
after data is read from FIFO.
0: Endpoint 0 FIFO is available for data receiving
FFRST0: Reset endpoint 0 FIFO read/write pointer
Write “1” to this bit will reset endpoint 0 FIFO read/write pointer. Data in endpoint 0 FIFO remain
unchanged. Before data are written into endpoint 0 FIFO, FFRST0 should be written first.
TXSEQ0: Endpoint 0 transmitting data sequence bit
1: Transmitting data use DATA1 as PID
0: Transmitting data use DATA0 as PID
TXOE0: Endpoint 0 FIFO data ready bit
1: Data has been received by endpoint 0
0: Data has not been received by endpoint 0
R/W
R/W
DADR4
R/W
DADR3
R/W
DADR2
R/W
DADR1
R/W
DADR0
R/O
R/O
R/W
TXCNT3
R/W
TXCNT2
R/W
TXCNT1
R/W
TXCNT0
RXCNT0
R/W
TXCNT3
R/W
TXCNT2
R/W
TXCNT1
R/W
TXCNT0
R/W
TXOE1
R/W
RXDIS0
W/O
FFRST0
R/W
TXSEQ0
R/W
TXOE0
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