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參數(shù)資料
| 型號： | GL424-WOGXX |
| 廠商： | Genesys Logic, Inc. |
| 英文描述： | SD/MMC Flash Card Controller |
| 中文描述： | SD / MMC卡閃存卡控制器 |
| 文件頁數(shù)： | 9/34頁 |
| 文件大?。?/td> | 506K |
| 代理商： | GL424-WOGXX |
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GL424 SD/MMC Flash Card Controller
2000-2007 Genesys Logic Inc. - All rights reserved.
Page 9
CHAPTER 2 FEATURES
2.1 SD Host Interface
Complies with SD Specification, Version 2.0
DMA operation between buffers and flash memory
Supports SPI mode and CPRM functions
2.3 Flash Memory Interface
Complies with SD Specification, Version 1.1
Supports automatic CRC16 generation and verification on DATA3-0
Supports clock rate up to 20 MHz for MMC3.3
Direct interface to NAND/AND flash chips (SAMSUNG / TOSHIBA / HITACHI / RENESAS /
Powerful ECC for error detection and correction up to 6 bytes per 512bytes
Complies with SD Specification, Version 1.0
Supports SD card exceed 4Gbytes capacity
Supports clock rate up to 52 MHz for MMC4.0
MICRON / ST / HYNIX)
Supports SPI mode and CPRM functions
Supports clock rate up to 25 MHz for SD1.0
2.2 MMC Host Interface
Supports clock rate up to 52 MHz for SD1.1 and SD2.0
Complies with MultiMediaCard System Specification, Version 4.0
Supports automatic CRC16 generation and verification on DATA7-0
Supports 64M / 128M / 256M / 512M / 1G / 2G / 4G / 8G bits flash chips
Buffers for multi-block flash memory programming
Complies with MultiMediaCard System Specification, Version 3.3
Buffers for multi-block flash memory programming
Supports dual-channel, 16 bits flash (VFBGA54 package and die)
DMA operation between buffers and flash memory
Drives up to 4 flash memory chips, respectively (VFBGA54 package and die)
Embedded firmware support for flash file system (FTL)
Built-in flash management algorithm
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