參數(shù)資料
型號(hào): GD16132-GLP
英文描述: ATM Multiplexer
中文描述: ATM多路復(fù)用器
文件頁(yè)數(shù): 9/11頁(yè)
文件大?。?/td> 114K
代理商: GD16132-GLP
Counter-directional Clocking Schema – GD16131/GD16054
Symbol:
Characteristic:
Conditions:
MIN.:
TYP.:
MAX.:
UNIT:
T
bd
Board propagation delay between GD16554
and GD16131 (sum of clock and data del.)
Note 1
0
400
ps
T
su
GD16054 Data Input set-up from Clock Output
Note 1
280
400
600
ps
T
ho
GD16054 Data Input hold from Clock Output
Note 1
-175
-250
-375
ps
T
cd
GD16131 Data Output from Clock Input
Note 1
300
530
920
ps
Note 1:
The above figures are based on layout parameters extractions and best assumptions. They give a hint of the magnitude
of the figures and feasibility of the Counter-Directional clocking method. The maximal
T
bd
is calculated as follows:
T
bd
max
=
T
bda
max
+
T
bdb
max
= 1.5 × 1/622MHz – 4 × (
T
pack
+
T
bond
) –
T
su
max
T
cd
max
0 >
T
bd
min
= 0.5 × 1/622MHz – 4 × (
T
pack
+
T
bond
) +
T
ho
min
T
cd
min
All efforts to keep
T
cd
as low as possible have been made. Please note that
T
bd
is the total round-trip board delay for both
clock and data path.
Data Sheet Rev.: 12
GD16131/GD16132
Page 9 of 11
Tcd
Tsu
Tbdb
Tho
Tbda
CK04
D40..43 (spec.)
CKIP
GD16054
GD16131
GD16131
GD16054
DOxP/N
D40..43
100ps
Bond
Wires
Bond
Wires
Package
Board
GD16131
GD16054
D40..43
CK04
DO0...3
CKI
Package
100ps
20ps
Anticipated Board Delay
250ps
On-chip Delay CK - Data
1000ps WC
20ps
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