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參數(shù)資料
| 型號(hào)： | GBP32 |
| 英文描述： | The GigaBridge Switched-PCI Controller|GBP Reset Design Note |
| 中文描述： | 在GigaBridge開(kāi)關(guān)PCI控制器|英鎊復(fù)位設(shè)計(jì)筆記 |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大?。?/td> | 275K |
| 代理商： | GBP32 |
7. Primary Node implementation in a CPLD (Verilog)
// This is the delay-and-flip flop power-up solution proposed mid-June of 2002.
// This is for Primary node power-up only.
module PorPrim (Clk,Prst_N,ResetOut_N,ClusMgrIn, Lrsti_N,Por_N,ClusMgr);
input Clk;
input Prst_N;
input ResetOut_N;
input ClusMgrIn;
output Lrsti_N;
output Por_N;
output ClusMgr;
reg Por_N;
reg Lrsti_N;
reg porRstN;
reg ClusMgr;
reg lrstiRstN;
reg [13:0] lrstiNdelay1; // 16 msec timer
reg [10:0] lrstiNdelay2; // 2 msec timer
reg [10:0] lrstiNdelay3; // another 2 msec timer
wire Del1done = &lrstiNdelay1; //Del1done goes high and stays high 16 msec after Lrsti_N first goes high
wire Del2done = &lrstiNdelay2; //Del2done goes high and stays high 2 msec after DEL1done first goes high
wire Del3done = &lrstiNdelay3; //Del3done goes high and stays high 2 msec after Del2done first goes high
wire DeAsrtPorN = Del2done & ~Del3done;
wire SecPorN = ~(~Del2done & Del1done & ClusMgrIn);
wire Lrsti_gen = ~(~Del3done & Del1done & ClusMgrIn);
wire EnPorN = ~Prst_N | DeAsrtPorN;
// 16 msec delay from assertion of Lrsti_N
always @(posedge Clk or negedge ResetOut_N)
begin
if (!ResetOut_N) lrstiNdelay1 <= 14'b0;
else if (Lrsti_N & ~Del1done) lrstiNdelay1 <= lrstiNdelay1 + 1'b1;
end
// 2 msec delay from assertion of Del1done
always @(posedge Clk or negedge ResetOut_N)
begin
if(!ResetOut_N) lrstiNdelay2 <= 11'b0;
else if (Del1done & ~Del2done) lrstiNdelay2 <= lrstiNdelay2 + 1'b1;
end
// 2 msec delay from assertion of Del2done
always @(posedge Clk or negedge ResetOut_N)
GBP/Reset Design Note v1.0
2002 PLX Technology, Inc. All rights reserved.
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