Specifications GAL16V8 5 In the Registered mode, macrocells are configured as dedicated registered outputs or as I/O functions. Architecture co" />
參數(shù)資料
型號(hào)： GAL16V8D-15LJN
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 24/26頁
文件大小： 0K
描述： SPLD 62.5MHZ EECMOS 20 PLCC
產(chǎn)品變化通告： Product Discontinuation 07/Sept/2010
標(biāo)準(zhǔn)包裝： 460
可編程類型： EE PLD
宏單元數(shù)： 8
輸入電壓： 4.75 V ~ 5.25 V
速度： 15ns
安裝類型： 表面貼裝
封裝/外殼： 20-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 20-PLCC（9x9）
包裝： 托盤
其它名稱： Q6536526
Specifications GAL16V8
5
In the Registered mode, macrocells are configured as dedicated
registered outputs or as I/O functions.
Architecture configurations available in this mode are similar to the
common 16R8 and 16RP4 devices with various permutations of
polarity, I/O and register placement.
All registered macrocells share common clock and output enable
control pins. Any macrocell can be configured as registered or I/
O. Up to eight registers or up to eight I/O's are possible in this mode.
Dedicated input or output functions can be implemented as sub-
sets of the I/O function.
Registered outputs have eight product terms per output. I/O's have
seven product terms per output.
The JEDEC fuse numbers, including the User Electronic Signature
(UES) fuses and the Product Term Disable (PTD) fuses, are shown
on the logic diagram on the following page.
Registered Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=0 defines this output configuration.
- Pin 1 controls common CLK for the registered outputs.
- Pin 11 controls common OE for the registered outputs.
- Pin 1 & Pin 11 are permanently configured as CLK &
OE for registered output configuration.
Combinatorial Configuration for Registered Mode
- SYN=0.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this output configuration.
- Pin 1 & Pin 11 are permanently configured as CLK &
OE for registered output configuration.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
DQ
Q
CLK
OE
XOR
Registered Mode
ALL
DEVICES
DISCONTINUED
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參數(shù)描述
GAL16V8D-15LJNI 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 16 INPUT 8 OUTPUT 5V LOW POWER 15ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
GAL16V8D15LP 制造商:Lattice Semiconductor Corporation 功能描述:
GAL16V8D-15LP 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 5V 16 I/O RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
GAL16V8D-15LPI 功能描述:SPLD - 簡(jiǎn)單可編程邏輯器件 16 Input 8 Output 5V Low Power 15ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池?cái)?shù)量:10 最大工作頻率:66 MHz 延遲時(shí)間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24
GAL16V8D15LPN 制造商:Lattice Semiconductor Corporation 功能描述:CMOS GAL EEPLD 16V8 DIP20 5.25V
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