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參數(shù)資料
| 型號： | G766 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 溫度/濕度傳感器 |
| 英文描述： | Remote Temperature Sensor with SMBus Serial Interface |
| 中文描述： | 遠(yuǎn)程溫度傳感器，帶有SMBus串行接口 |
| 文件頁數(shù)： | 11/13頁 |
| 文件大?。?/td> | 248K |
| 代理商： | G766 |
Ver 1.0
Dec 11, 2001
TEL: 886-3-5788833
http://www.gmt.com.tw
11
Global Mixed-mode Technology Inc.
G766
Table 7. Conversion-Rate Control Byte
DATA
00h
01h
02h
03h
04h
05h
06h
07h
08h to FFh
CONVERSION RATE (Hz)
0.0125
0.25
0.5
1
2
4
8
16
RFU
To check for internal bus collisions, read the status byte. If
the least significant seven bits are ones, discard the data
and read the status byte again. The status bits RHIGH,
and RLOW are refreshed on the SMBus clock edge im-
mediately following the stop condition, so there is no dan-
an internal bus collision. The OPEN status bit (diode con-
tinuity fault) is only refreshed at the beginning of a conver-
sion, so OPEN data is lost. The ALERT interrupt latch is
independent of the status byte register, so no false alerts
are generated by an internal bus collision.
When auto-converting, if the THIGH and TLOW limits are
close together, it’s possible for both high-temp and
low-temp status bits to be set, depending on the amount
of time between status read operations (especially when
converting at the fastest rate). In these circumstances, it’s
best not to rely on the status bits to indicate reversals in
long-term temperature changes and instead use a cur-
rent temperature reading to establish the trend direction.
Conversion Rate Byte
The conversion rate register (Table 7) programs the
time interval between conversions in free-running
auto-convert mode. This variable rate control reduces
the supply current in portable-equipment applications.
The conversion rate byte’s POR state is 07h (16Hz).
Slave Addresses
The G766 appears to the SMBus as one device hav-
ing a common address for both ADC channels. The
device address can be set to one of nine different val-
ues by pin-strapping ADD0 and ADD1 so that more
than one G766 can reside on the same bus without
address conflicts (Table 8).
The address pin states are checked at POR only, and
the address data stays latched to reduce quiescent
supply current due to the bias current needed for
high-Z state detection.
The G766 also responds to the SMBus Alert Re-
sponse slave address (see the Alert Response Ad-
dress section).
POR and UVLO
The G766 has a volatile memory. To prevent ambigu-
ous power-supply conditions from corrupting the data
in memory and causing erratic behavior, a POR volt-
age detector monitors Vcc and clears the memory if
Vcc falls below 1.7V (typical, see Electrical Character-
istics table). When power is first applied and Vcc
rises above 1.75V (typical), the logic blocks begin op-
erating, although reads and writes at V
CC
levels below
3V are not recommended. A second Vcc comparator,
the ADC UVLO comparator, prevents the ADC from
converting until there is sufficient headroom (Vcc =
2.8V typical).
Table 8. Slave Address Decoding
(ADD0 and ADD1)
ADD0
GND
GND
GND
High-Z
High-Z
High-Z
Vcc
Vcc
Vcc
ADD1
GND
High-Z
Vcc
GND
High-Z
Vcc
GND
High-Z
Vcc
ADDRESS
0011 000
0011 001
0011 010
0101 001
0101 010
0101 011
1001 100
1001 101
1001 110
Note: High-Z means that the pin is left unconnected
and floating.
Power-Up Defaults:
Interrupt latch is cleared.
Address select pins are sampled.
T
HIGH
and T
LOW
registers are set to max and min
limits, respectively.
Device is in normal mode. ( ALERT acts as a
latched interrupt output.)
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