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參數(shù)資料
| 型號： | G709E2-5 |
| 英文描述： | G709E2-5 2.5 Gbits/sec ITU G.709 Reed-Solomon Encoder Core |
| 中文描述： | G709E2 - 5 2.5 Gbits / sec的國際電聯(lián)支持G.709的Reed - Solomon編碼器核心 |
| 文件頁數(shù)： | 4/4頁 |
| 文件大?。?/td> | 142K |
| 代理商： | G709E2-5 |
comtech
aha
corporation
Page 2 of 2
A subsidiary of Comtech Telecommunications Corporation
PSFECEncoderCore_0702
3.0
SIGNAL DESCRIPTIONS
3.1
INPUT INTERFACE
3.2
OUTPUT INTERFACE
4.0
TIMING DIAGRAMS
Figure 2:
FUNCTIONAL TIMING
Signal
Type
I
Description
DATA[7:0]
Data Bus. Input data bus for information word.
Block start signal. This signal is asserted with the first byte
transfer of a block. Start signals should be at least 255 clocks
apart, but can be more than 255 clocks.
System Clock.
Global Reset. When active (high) RESET forces a reset on all of
the flip-flops involved in parity generation.
START
I
CLK
I
RESET
I
Signal
Type
Description
OUT[7:0]
O
Output data bus. Message Bytes are passed through onto this
bus followed by the 16 parity check bytes for each 239 Byte
block that is processed.
1
2
3
239
238
237
r15
r14
r13
r12
r1
r2
r0
1
2
1
2
3
4
5
239
1
2
3
4
CLK
RESET
START
DATA
OUT
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