參數(shù)資料
型號: G571
廠商: Electronic Theatre Controls, Inc.
英文描述: Single-Slot PCMCIA/CardBus Power Controllers
中文描述: 單插槽的PCMCIA / CardBus電源控制器
文件頁數(shù): 4/11頁
文件大小: 151K
代理商: G571
Ver 1.1
Jan 08, 2001
TEL: 886-3-5788833
http://www.gmt.com.tw
4
G571
Global Mixed-mode Technology Inc.
Logic Section
PARAMETER
TEST CONDITION*
MIN
2
MAX UNIT
1
0.8
0.4
Logic input current
Logic input high level
Logic input low level
V
I(5V)
= 5V, I
O
=1mA
V
I(5V)
=0V,I
O
= 1mA,V
I(3.3V)
= 3.3V
I
O
= 1mA
μA
V
V
V
I(5V)
- 0.4
V
I(3.3V)
- 0.4
Logic output high level
V
Logic output low level
V
*Pulse-testing techniques maintain junction temperature close to ambient temperatures; thermal effects must be taken into account separately.
Switching Characteristics **
PARAMETER
TEST CONDITION
MIN
TYP
2.6
10
7.5
38
14
44
3.2
17
4.4
20
MAX
UNIT
V
O (AVCC)
V
O (AVPP)
V
O (AVCC)
V
O (AVPP)
t
r
Rise times, output
t
f
Fall times, output
ms
t
on
t
off
t
on
t
off
t
on
t
off
V
I
(
VPPD0
) to V
O(AVPP)
V
I
(
1
VCCD
) to V
O(AVCC)
(3.3V)
t
pd
Propagation delay
(see Figure 1)
V
I
(
0
VCCD
) to V
O(AVCC)
(5V)
ms
**Switching Characteristics are with C
L
= 147μF.
§ Refer to Parameter Measurement Information
Parameter Measurement Information
Figure 1. Test Circuits and Voltage Waveforms
Table of Timing Diagrams
AVCC Propagation Delay and Rise Time With 1μF Load, 3.3V Switch
AVCC Propagation Delay and Fall Time With 1μF Load, 3.3V Switch
AVCC Propagation Delay and Rise Time With 147μF Load, 3.3V Switch
AVCC Propagation Delay and Fall Time With 147μF Load, 3.3V Switch
AVCC Propagation Delay and Rise Time With 1μF Load, 5V Switch
AVCC Propagation Delay and Fall Time With 1μF Load, 5V Switch
AVCC Propagation Delay and Rise Time With 147μF Load, 5V Switch
AVCC Propagation Delay and Fall Time With 147μF Load, 5V Switch
AVPP Propagation Delay and Rise Time With 1μF Load, 12V Switch
AVPP Propagation Delay and Fall Time With 1μF Load, 12V Switch
AVPP Propagation Delay and Rise Time With 147μF Load, 12V Switch
AVPP Propagation Delay and Fall Time With 147μF Load, 12V Switch
FIGURE
2
3
4
5
6
7
8
9
10
11
12
13
LOAD CIRCUIT
V
DD
GND
50%
90%
t
off
t
on
10%
V
I(12V)
GND
V
O(AVPP)
AVPP
C
L
VOLTAGE WAVEFORMS
50%
V
I(VPPD0)
(V
I(VPPD1)
=0V)
LOAD CIRCUIT
V
DD
GND
50%
90%
t
off
t
on
10%
V
I(3.3V)
GND
V
O(AVCC)
AVCC
C
L
VOLTAGE WAVEFORMS
V
I(VCCD1)
(V
I(VCCD0)
=V
DD
)
50%
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