參數(shù)資料
型號(hào): G2996
英文描述: DDR Termination Regulator with STR function.|Terminator Series
中文描述: 復(fù)員與STR函數(shù)終端調(diào)節(jié)。|終結(jié)者系列
文件頁(yè)數(shù): 10/12頁(yè)
文件大?。?/td> 323K
代理商: G2996
Ver: 1.0
May 23, 2003
TEL: 886-3-5788833
http://www.gmt.com.tw
10
G2996
Global Mixed-mode Technology Inc.
In Figure 5 & 6, they are the application configurations
of DDR-II SDRAM bus terminations. Figure 5 is the
typical application scheme of DDR-II SDRAM. With
the separate VDDQ pin and an internal resistor divider,
it is possible to use the G2996 in applications utilizing
DDR-II memory. Figure 6 is used to increase the driv-
ing capability. The risk is the same as figure 4.
Figure 7 & 8 are used to scale the V
TT
to the wanted
value when the standard voltages of SSTL-2 do not
meet the requirements. Using R1 & R2, figure 7 can
shift V
TT
up to VDDQ/2 * (1+R1/R2) and figure 8 can
shift V
TT
down to VDDQ/2 * (1-R1/R2).
+
+
V
DDQ
AV
IN
V
SENSE
PV
IN
V
TT
GND
V
TT
V
DD
C
IN
Figure 7. Increasing VTT by Level Shifting
C
OUT
V
DDQ
R1
R2
+
+
V
DDQ
AV
IN
V
SENSE
PV
IN
V
TT
GND
V
TT
V
DD
C
IN
Figure 8. Decreasing VTT by Level Shifting
C
OUT
V
DDQ
R1
R2
+
+
+
SD
V
REF
V
DDQ
AV
IN
V
SENSE
PV
IN
V
TT
GND
V
TT
=0.9V
C
REF
V
DDQ
=1.8V
AV
IN
=2V or 5.5V
SD
C
IN
Figure 5. Recommended DDR-II Termination
C
OUT
PV
IN
=1.8V
+
+
+
SD
V
REF
V
DDQ
AV
IN
V
SENSE
PV
IN
V
TT
GND
V
TT
=0.9V
C
REF
V
DDQ
=1.8V
AV
IN
=3.3V or 5.5V
SD
C
IN
Figure 6. DDR-II Termination with higher voltage rails
C
OUT
PV
IN
=3.3V
V
REF
=0.9V
V
REF
=0.9V
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