
2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FXMA2102
Rev. 1.0.6
6
F
XM
A
2102
—
Dual
-S
upply
,
2
-Bit
Vol
tage
Tra
nsl
a
to
r/
Buf
fer
/
Repe
a
ter
/
Is
ola
to
rfor
I
2
C
Ap
plic
a
tions
Application Notes
The FXMA2102 has open-drain I/Os and requires
external pull-up resistors on the four data I/O pins, as
shown in Figure 4. If a pair of data I/O pins (An/Bn) is not used, both pins should be tied to GND (or both to VCC).
In this case, pull-down or pull-up resistors are not
required. The recommended values for the pull-up
resistors (RPU) are 1
K to 10 K; however, depending
on the total bus capacitance, the user is free to vary the
pull-up resistor value to meet the maximum I
2C edge
rate per the I
2C specification (UM10204 rev. 03, June
19, 2007). For example, the maximum edge rate (30% -
70%) during fast mode (400 kbit/s) is 300 ns. If bus
capacitance is approaching the maximum 400 pF, lower
the RPU value to keep the rise time below 300 ns (Fast
Mode). Section 7.1 of the I
2C specification provides an
excellent guideline for pull-up resistor sizing.
Theory of Operation
The FXMA2102 is designed for high-performance level
shifting and buffer / repeating in an I
2C application.
shows
that
each
bi-directional
channel
contains two series-Npassgates and two dynamic
drivers. This hybrid architecture is highly beneficial in an
I
2C application where auto-direction is a necessity.
For example, during the following three I
2C protocol
events:
Clock Stretching
Slave’s ACK Bit (9
th bit = 0) following a Master’s
Write Bit (8
th bit = 0)
Clock Synchronization and Multi Master
Arbitration
the bus direction needs to change from master to slave
to slave to master without the occurrence of an edge. If
there is an I
2C translator between the master and slave
in these examples, the I
2C translator must change
direction when both A and B ports are LOW. The
Npassgates can accomplish this task very efficiently
because, when both A and B ports are LOW, the
Npassgates act as a low resistive short between the two
(A and B) ports.
Due to I
2C’s open-drain topology, I2C masters and
slaves are not push/pull drivers. Logic LOWs are
“pulled down” (Isink), while logic HIGHs are “l(fā)et go” (3-
state). For example, when the master lets go of SCL
(SCL always comes from the master), the rise time of
SCL is largely determined by the RC time constant,
where R = RPU and C = the bus capacitance. If the
FXMA2102 is attached to the master [on the A port] in
this example, and there is a slave on the B port, the
Npassgates act as a low resistive short between both
ports until either of the port’s VCC/2 thresholds are
reached. After the RC time constant has reached the
VCC/2 threshold of either port, the port’s edge detector
triggers both dynamic drivers to drive their respective
ports in the LOW-to-HIGH (LH) direction, accelerating
the rising edge. The resulting rise time resembles the
scope shot in
Figure 5. Effectively, two distinct slew
rates appear in rise time. The first slew rate (slower) is
the RC time constant of the bus. The second slew rate
(much faster) is the dynamic driver accelerating the
edge.
If both the A and B ports of the translator are HIGH, a
high-impedance path exists between the A and B ports
because both the Npassgates are turned off. If a master
or slave device decides to pull SCL or SDA LOW, that
device
’s driver pulls down (Isink) SCL or SDA until the
edge reaches the A or B port VCC/2 threshold. When
either the A o
r B port threshold is reached, the port’s
edge detector triggers both dynamic drivers to drive
their
respective
ports
in
the
HIGH-to-LOW
(HL)
direction, accelerating the falling edge.
Figure 5. FXMA2102 Waveform C: 600 pF, RPU: 2.2 K