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參數(shù)資料
| 型號： | FXMA108BQX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 4/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | TRANSLATOR 8BIT DUAL 3ST 20DQFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 邏輯功能： | 變換器，雙向，單向，3 態(tài) |
| 位數(shù)： | 8 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 數(shù)據(jù)速率： | 80Mbps |
| 通道數(shù)： | 8 |
| 輸出/通道數(shù)目： | 1 |
| 差分 - 輸入:輸出： | 無/無 |
| 傳輸延遲（最大）： | 5.5ns |
| 電源電壓： | 1.65 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 20-WQFN 裸露焊盤，20-DQFN |
| 供應(yīng)商設(shè)備封裝： | 20-DQFN |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | FXMA108BQXDKR FXMA108BQXDKR-ND FXMA108BQXFSDKR |
2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FXMA108 Rev. 1.0.1
12
FXMA108
—
Dual-Supply,
8-Bit
Signal
Translator
with
Configurable
Voltage
S
upplies
and
Signal
Levels
I/O Architecture Benefit
The FXMA108 I/O architecture benefits the end user,
beyond level translation, in the following three ways:
Auto Direction
without an external direction pin.
Drive Capacitive Loads
. Automatically shifts to a
higher current drive mode only during “Dynamic Mode”
or HL / LH transitions.
Lower Power Consumption
. Automatically shifts to
low-power mode during “Static Mode” (no transitions),
lowering power consumption.
The FXMA108 does not require a direction pin. Instead,
the I/O architecture detects input transitions on both
side and automatically transfers the data to the
corresponding output. For example, for a given channel,
if both A and B side are at a static LOW, the direction
has been established as A
B, and a LH transition
occurs on the B port; the FXMA108 internal I/O
architecture automatically changes direction from A
B to B
A.
During HL / LH transitions, or “Dynamic Mode,” a strong
(typically 30mA) output driver drives the output channel
in parallel with a weak (typically 100A) output driver.
After a typical delay of approximately 10ns – 50ns, the
strong driver is turned off, leaving the weak driver
enabled for holding the logic state of the channel. This
weak driver is called the “bus hold.” “Static Mode” is
when only the bus hold drives the channel. The bus
hold can be over ridden (typically 500A) in the event of
a direction change. The strong driver allows the
FXMA108 to quickly charge and discharge capacitive
transmission lines during dynamic mode. Static mode
conserves power, where ICC is typically < 5A.
Bus Hold Minimum Drive Current
Specifies the minimum amount of current the bus hold
driver can source/sink. The bus hold minimum drive
current (IHOLD) is VCC dependent and guaranteed in the
DC Electrical tables. The intent is to maintain a valid
output state in a static mode, but that can be overridden
when an input data transition occurs.
Bus Hold Input Overdrive Drive Current
Specifies the minimum amount of current required (by
an external device) to overdrive the bus hold in the
event of a direction change. The bus hold overdrive
(IODH, IODL) is VCC dependent and guaranteed in the DC
Electrical tables.
Dynamic Output Current
The strength of the output driver during LH / HL
transitions is captured in Figure 3 (IOLH, IOHD). The plot
depicts the FXMA108 typical dynamic output current
with a lumped capacitance of 4pF.
Because the strong output driver is turned on only
during LH / HL transitions, the actual drive current is
difficult to measure directly. Approximate the drive
current with the following formula:
RISE
CCO
O
I
OUT
O
I
OHD
t
V
C
t
V
C
I
*
6
.
0
)
(
)
(
/
×
=
Δ
×
≈
(1)
where
CI/O = the typical lumped capacitance and
VCCO is the supply voltage of the output driver.
Figure 3.
Typical Dynamic Output Current
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| FXMA2102UMX | 功能描述:轉(zhuǎn)換 - 電壓電平 2xSupply 2-Bit Volt Trnsltr/Bffr/Rptr RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
| FXMA2102UMX_F106 | 功能描述:轉(zhuǎn)換 - 電壓電平 Config Volt Xlator RoHS:否 制造商:Micrel 類型:CML/LVDS/LVPECL to LVCMOS/LVTTL 傳播延遲時間:1.9 ns 電源電流:14 mA 電源電壓-最大:3.6 V 電源電壓-最小:3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MLF-8 |
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