參數(shù)資料
型號(hào)： FXLP34L6X
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 其它接口
英文描述： Single Bit Uni-Directional Translator
中文描述： SPECIALTY INTERFACE CIRCUIT, PDSO6
封裝： 1 MM, MO-252UAAD, MICROPAK-6
文件頁(yè)數(shù)： 6/11頁(yè)
文件大?。?/td> 322K
代理商： FXLP34L6X
www.fairchildsemi.com
6
F
AC Electrical Characteristics
(Continued)
Translator Power Up Sequence Recommendations
To insure that the system does not experience unneces-
sary I
CC
current draw, bus contention or oscillations during
power up, the following guidelines should be adhered to.
This device is designed with the Output pin(s) is supplied
by V
CC
and the Input pin(s) is supplied by V
CC1
. Therefore
the first recommendation is to begin by powering up the
input side of the device, V
CC1
. The Input pin(s) should be
ramped with or ahead of V
CC1
or held LOW. This will guard
against bus contentions and oscillations as all Inputs and
the Input V
CC1
will be powered at the same time. The Out-
put V
CC
can then be powered to the voltage level that the
device will be used to translate to. The Output pin(s) will
then translate to logic levels dictated by the Output V
CC
levels.
Upon completion of these steps the device can then be
configured for the users desired operation. Following these
steps will help to prevent possible damage to the translator
device as well as other system components.
Symbol
Parameter
V
CC1
(V)
1.0
T
A
=
+
25
°
C
Typ
22.0
19.0
T
A
=
40
°
C to
+
85
°
C
Min
Units
Conditions
Figure
Number
Min
Max
Max
t
PHL
t
PLH
Propagation Delay
Output Translation
V
CC
(V)
=
1.2
ns
Figures
1, 2
1.10 to 1.30
11.0
29.0
10.0
46.5
1.40 to 1.60
1.65 to 1.95
2.30 to 2.70
10.0
9.0
8.5
18.0
17.0
16.0
27.5
26.7
26.1
9.0
8.0
7.0
42.6
36.7
36.0
C
L
=
30 pF
R
L
=
1 M
3.00 to 3.60
1.0
1.10 to 1.30
8.0
16.0
16.0
13.0
26.0
6.0
35.9
t
PHL
t
PLH
Propagation Delay
Output Translation
V
CC
(V)
=
1.5
ns
Figures
1, 2
6.0
19.8
5.5
25.3
1.40 to 1.60
1.65 to 1.95
2.30 to 2.70
5.8
5.5
5.0
12.0
11.0
10.0
18.3
17.6
17.0
5.0
4.5
4.0
23.0
22.4
21.7
C
L
=
30 pF
R
L
=
1 M
3.00 to 3.60
1.0
1.10 to 1.30
4.5
9.0
15.0
11.0
16.8
3.5
21.5
t
PHL
t
PLH
Propagation Delay
Output Translation
V
CC
(V)
=
1.8
ns
Figures
1, 2
5.0
16.2
5.5
20.4
1.40 to 1.60
1.65 to 1.95
2.30 to 2.70
4.5
4.0
3.5
10.0
9.0
8.0
14.7
13.9
13.3
4.0
3.5
3.0
19.2
18.5
17.9
C
L
=
30 pF
R
L
=
1 M
3.00 to 3.60
1.0
1.10 to 1.30
3.5
8.0
13.0
8.0
13.1
2.5
17.6
t
PHL
t
PLH
Propagation Delay
Output Translation
V
CC
(V)
=
2.5
ns
Figures
1, 2
4.0
12.7
3.5
15.9
1.40 to 1.60
1.65 to 1.95
2.30 to 2.70
3.5
3.0
2.5
7.0
6.0
5.0
11.2
10.5
9.9
3.0
2.5
2.0
14.3
13.6
12.8
C
L
=
30 pF
R
L
=
1 M
3.00 to 3.60
1.0
2.5
5.0
12.0
9.7
2.0
12.5
t
PHL
t
PLH
Propagation Delay
ns
Figures
1, 2
Output Translation
V
CC
(V)
=
3.3
1.10 to 1.30
1.40 to 1.60
1.65 to 1.95
3.0
2.5
2.0
8.0
7.0
6.0
11.7
9.8
8.9
2.0
1.5
1.0
15.0
12.2
11.5
C
L
=
30 pF
R
L
=
1 M
2.30 to 2.70
3.00 to 3.60
0
1.5
1.5
5.0
5.0
2.0
8.3
8.1
1.0
1.0
10.7
10.4
C
IN
C
OUT
C
PD
Input Capacitance
pF
Output Capacitance
Power Dissipation
Capacitance
0
4.0
pF
V
CC
/V
CC1
=
(1.0 to 3.60)
8.0
pF
V
I
=
0V or V
CC1
f
=
10 MHz
V
CC
/V
CC1
=
3.6
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