參數(shù)資料
型號(hào): FXLA102L8X
廠商: Fairchild Semiconductor
文件頁數(shù): 13/17頁
文件大?。?/td> 0K
描述: TRANSLATOR DUAL 2BIT 8-MICROPAK
標(biāo)準(zhǔn)包裝: 1
邏輯功能: 變換器,雙向,3 態(tài)
位數(shù): 2
輸入類型: 電壓
輸出類型: 電壓
數(shù)據(jù)速率: 140Mbps
通道數(shù): 1
輸出/通道數(shù)目: 2
差分 - 輸入:輸出: 無/無
傳輸延遲(最大): 3.5ns
電源電壓: 1.1 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-XFQFN
供應(yīng)商設(shè)備封裝: 8-MicroPak?
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 1219 (CN2011-ZH PDF)
其它名稱: FXLA102L8XDKR
FXLA102L8XDKR-ND
FXLA102L8XFSDKR
2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FXLA102 Rev. 1.0.4
5
FXLA102
Low-Voltage
Dual-Suppl
y
2-Bit
Voltage
Translator
Power-Up/Power-Down Sequence
FXL translators offer an advantage in that either VCC
may be powered up first. This benefit derives from the
chip design. When either VCC is at 0 V, outputs are in a
high-impedance state. The control input (/OE) is
designed to track the VCCA supply. A pull-up resistor
tying /OE to VCCA should be used to ensure that bus
contention, excessive currents, or oscillations do not
occur during power-up or power-down. The size of the
pull-up resistor is based upon the current-sinking
capability of the device driving the /OE pin.
The recommended power-up sequence is:
1.
Apply power to the first VCC.
2.
Apply power to the second VCC.
3.
Drive the /OE input LOW to enable the device.
The recommended power-down sequence is:
1.
Drive /OE input HIGH to disable the device.
2.
Remove power from either VCC.
3.
Remove power from other VCC.
Pull-Up/Pull-Down Resistors
Do not use pull-up or pull-down resistors. This device
has bus-hold circuits: pull-up or pull-down resistors are
not recommended because they interfere with the
output state. The current through these resistors may
exceed the hold drive, II(HOLD) and/or II(OD) bus-hold
currents. The bus-hold feature eliminates the need for
extra resistors.
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