參數(shù)資料
型號: FXL5T244BQX
廠商: Fairchild Semiconductor
文件頁數(shù): 2/8頁
文件大小: 0K
描述: TRANSLATOR 5BIT DUAL LV 14DQFN
產(chǎn)品培訓(xùn)模塊: Logic Translator Solutions
標(biāo)準(zhǔn)包裝: 1
邏輯功能: 變換器,雙向,3 態(tài)
位數(shù): 5
輸入類型: 電壓
輸出類型: 電壓
通道數(shù): 1
輸出/通道數(shù)目: 5
差分 - 輸入:輸出: 無/無
傳輸延遲(最大): 3.5ns
電源電壓: 1.1 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
封裝/外殼: 14-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 14-DQFN
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 1223 (CN2011-ZH PDF)
其它名稱: FXL5T244BQXDKR
www.fairchildsemi.com
2
FXL5T244
Terminal Descriptions
Truth Table
H
= HIGH Voltage Level
L
= LOW Voltage Level
X
= Don’t Care
Connection Diagram
Terminal Assignments for DQFN
(Top View)
Terminal Assignment
Power-Up/Power-Down Sequencing
FXL translators offer an advantage in that either VCC may
be powered up first. This benefit derives from the chip
design. When either VCC is at 0 volts, outputs are in a
HIGH-Impedance state. The control input, OE, is designed
to track the VCCI supply. A pull-up resistor tying OE to VCCI
should be used to ensure that bus contention, excessive
currents, or oscillations do not occur during power-up/
power-down. The size of the pull-up resistor is based upon
the current-sinking capability of the OE driver.
The recommended power-up sequence is the following:
1. Apply power to either VCC.
2. Apply power to the OE input (Logic HIGH for A-to-B
operation; Logic LOW for B-to-A operation) and to the
respective data inputs (A Port or B Port). This may
occur at the same time as Step 1.
3. Apply power to other VCC.
4. Drive the OE input LOW to enable the device.
The recommended power-down sequence is the following:
1. Drive OE input HIGH to disable the device.
2. Remove power from either VCC.
3. Remove power from other VCC.
Terminal
Names
Description
OE
Output Enable Input
An
Data Inputs
Yn
3-STATE Outputs
VCCI
Inputs Power Supply
VCCO
Outputs Power Supply
GND
Ground
Inputs
Outputs
OE
An
Yn
LLL
LH
H
HX
3-STATE
Terminal Number
Terminal Name
1VCCI
2A0
3A1
4A2
5A3
6A4
7GND
8OE
9Y4
10
Y3
11
Y2
12
Y1
13
Y0
14
VCCO
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