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參數(shù)資料
| 型號： | FW801A |
| 英文描述： | Low-Power PHY IEEE 1394A-2000 One-Cable Transceiver/Arbiter Device |
| 中文描述： | 低功耗PHY的IEEE 1394A端口，2000年一電纜收發(fā)器/仲裁器裝置 |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 378K |
| 代理商： | FW801A |
Data Sheet, Rev. 1
June 2001
FW801A Low-Power PHY
IEEE
1394A-2000
One-Cable Transceiver/Arbiter Device
Agere Systems Inc.
5
Description
(continued)
The SYSCLK output will become active (and the PHY/
link interface will be initialized and become operative)
within 3 ms after LPS is asserted high, when the
FW801A is in the low-power mode.
Two of the signals are used to set up various test con-
ditions used in manufacturing. These signals (SE and
SM) should be connected to V
SS
for normal operation.
5-5459.e (F)r.2
Figure 1. Block Diagram
LINK
INTERFACE
I/O
RECEIVED
DATA
DECODER/
RETIMER
ARBITRATION
AND
CONTROL
STATE
MACHINE
LOGIC
BIAS
VOLTAGE
AND
CURRENT
GENERATOR
OSCILLATOR,
PLL SYSTEM,
AND
CLOCK
GENERATOR
TRANSMIT
DATA
ENCODER
CABLE PORT 0
TPA0+
TPA0–
TPB0+
TPB0–
R0
R1
XI
XO
CPS
LPS
/ISO
CNA
SYSCLK
LREQ
CTL0
CTL1
D0
D1
D2
D3
D4
D5
D6
D7
C/LKON
SE
SM
PD
/RESET
CRYSTAL
TPBIAS0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FW801A-DB | Low-Power PHY IEEE 1394A-2000 One-Cable Transceiver/Arbiter Device |
| FW801 | One-Cable Transceiver/Arbiter Device |
| FW80200M400 | Microprocessor |
| FW80200M600 | Microprocessor |
| FW80200M733 | Microprocessor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FW801A-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:Low-Power PHY IEEE 1394A-2000 One-Cable Transceiver/Arbiter Device |
| FW801BF | 制造商:AGERE 制造商全稱:AGERE 功能描述:Low-Power PHY 1394a-2000 One-Cable Transceiver/Arbiter Device |
| FW801BF-09-DB | 制造商:AGERE 制造商全稱:AGERE 功能描述:Low-Power PHY 1394a-2000 One-Cable Transceiver/Arbiter Device |
| FW802 | 制造商:AGERE 制造商全稱:AGERE 功能描述:Low-Power PHY IEEE 1394A-2000 Two-Cable Transceiver/Arbiter Device |
| FW80200M400 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
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