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參數(shù)資料
| 型號： | FTS375 EVAL KIT |
| 廠商： | Connor-Winfield |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | GPS TIMING MODULE EVAL BOARD |
| 產品培訓模塊： | 125 Series GPS Based Timing and Synchronization Products |
| 標準包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器，同步器，GPS |
| 嵌入式： | 否 |
| 已用 IC / 零件： | FTS375 |
| 主要屬性： | 1PPS/ 10 MHz 相位校準功能 |
| 次要屬性： | LED 狀態(tài)指示器 |
| 已供物品： | 板，模塊 |
| 其它名稱： | CW689 |
Features
Phaselocked10MHzoutput
1PPSoutput
3selectablereferences:GPS,External10MHzorExternal1PPS
Holdover
Threealarmoutputs.(Loss-of-Lock,HoldoverandAntennaFault)
Serialinputandoutputports(GPSreceiver)
Masterreset
+3.3Voltpowersupply
CommercialTemp(0-70°C)
MechanicalDimensions:3.937”x1.969”x0.708”(100mmx50mmx17.98mm)
Package:36-pinThrough-Hole
FixedPositionUnit
125 Series FTS375
Disciplined Reference and
Synchronous Clock Generator
2111 Comprehensive Drive
Aurora, Illinois 60505
Phone: 630- 851- 4722
Fax: 630- 851- 5040
www.conwin.com
Bulletin
SG174
Revision
02
Date
03 Jan 12
Issued By
ENG
General Description
The FTS375 module is a GPS driven, mixed-signal phase
lock loop, providing a 1 PPS CMOS output from a Connor-
Winfield GPS timing receiver and generating a 10 MHz
CMOS and a 10 MHz SINE output from an intrinsically low
jitter voltage controlled crystal oscillator. The FTS375 can
lock to a 10 MHz reference derived from the on-board GPS
receiver or an external 10 MHz reference or to an external
1 PPS reference. Alarms are provided to indicate Loss-
of-Lock, Holdover, and Antenna Fault. The on-board GPS
receiver requires an outdoor mounted GPS antenna for the
best stability and consistent performance.
The mode control inputs are used to manually switch
between references and/or holdover. The user application
should monitor the alarm outputs and manually switch modes as needed.
Serial I/O lines provide access to the NMEA messages from the GPS receiver (referenced in the
Connor-Winfield’s Wi125 User Manual. Contact Connor-Winfield Sales for a copy). The serial I/O lines
can be used to access GPS timestamp information, or to verify that the receiver has recovered from an
alarm condition. The reset is used to reset the GPS receiver (if needed).
D
A
T
A
S
H
E
T
CPLD
ANALOG
FILTER
1 / N
LOW JITTER
OCVCXO
DRIVER
&
TRANSLATION
ANTENNNA FAULT STATUS
1 PPS CMOS OUTPUT
LOCK STATUS
HOLDOVER STATUS
SERIAL OUTPUT (A, B)
10 MHz CMOS
OUTPUT
10 MHz SINE
OUTPUT
DPFD
BOOT SEL
SERIAL IN
(A, B)
GPS REF
33
33
MCX
Connector
FTS375 Module
1 PPS
10 MHz REF
1 PPS REF
RESET
SYNC 1 CONTROL
SYNC 2 CONTROL
DISABLE
Wi125
(GPS Receiver)
OCXO
REFERENCE
JTAG
(Programming Only)
Functional Block Diagram
Figure 1
Available at Digi-Key
www.digikey.com
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