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參數(shù)資料
| 型號： | FTLX1671D3BCL |
| 元件分類： | 光收發(fā) |
| 英文描述： | FIBER OPTIC TRANSCEIVER, 1530-1565nm, 10000Mbps(Tx), 10000Mbps(Rx), SURFACE MOUNT, LC CONNECTOR |
| 封裝： | ROHS COMPLIANT PACKAGE |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 467K |
| 代理商： | FTLX1671D3BCL |
FTLX
Fini
II.
A
Exce
Maxim
Storag
Relativ
1.
N
III.
Supply
Trans
Input d
Differ
Transm
Receiv
Differ
Outpu
LOS F
LOS N
Power
Notes:
1.
C
2.
In
3.
20
fo
4.
L
op
5.
Se
6.
Th
us
th
IV.
Trans
Optica
(OMA
Avera
Optica
Side-M
Optica
Transm
Avera
transm
Tx Jitt
Relativ
X1671D3BCL
isar Corporatio
Absolute M
eding the lim
Pa
mum Supply V
ge Temperature
ve Humidity
Non-condensing
Electrical
Par
y Voltage
y Current
smitter
differential imp
rential data inpu
mit Disable Vo
mit Enable Vol
ver
rential data outp
ut rise time and
Fault
Normal
r Supply Noise
:
Connected direc
nto 100
Ω differ
0 – 80%. Mea
our 0’s sequenc
OS is an open
peration is logi
ee Section 2.8.
he FTLX1671D
sing an EDC P
he host-board E
Optical C
Parame
smitter
al Modulation A
A) minus TDP
age Launch Pow
al Wavelength
Mode Suppress
al Extinction R
mitter and Disp
age Launch pow
mitter
ter
ve Intensity No
SFP+ ER/EW
on - August 20
Maximum Ra
mits below m
arameter
Voltage
e
g.
Characteri
rameter
pedance
ut swing
oltage
ltage
put swing
d fall time
e Tolerance
ctly to TX data
rential termina
asured with Mo
ce in the PRBS
collector outpu
ic 0; loss of sig
.4 of SFF-8431
D3BCL is a “l(fā)
PHY IC should
EDC PHY with
Characterist
eter
Amplitude
wer
sion Ratio
Ratio
persion Penalty
wer of OFF
oise
W Specification
010
atings
may damage
istics (TOP = 0
V
a input pins. A
ation.
odule Complian
S 9 is an accept
ut. Should be p
gnal is logic 1.
1 Rev 4.1.
imiting module
follow the IC
h a limiting rec
tics (TOP = 0 t
Symbol
POMA-TDP
PAVE
λ
SMSR
ER
y
TDP
POFF
Txj
RIN
– August 2010
Rev. B1
the transcei
Symbol
Vcc
TS
RH
0 to 70
°C, V
C
Symbol
Vcc
Icc
Rin
Vin,pp
VD
VEN
Vout,pp
Tr, Tf
VLOS fault
VLOS norm
VccT/VccR
C coupling fro
nce Test Board
table alternativ
pulled up with
e”, i.e., it empl
manufacturer’
ceiver SFP+ mo
to 70
°C, V
CC3
l
Min
P
-2.1
-4.7
1530
30
3.0
0
ver module
Min
Typ
-0.5
-40
0
C = 3.14 to 3.4
Min
Typ
3.14
270
100
180
2
Vee
300
28
2
Vee
Per SFF-84
om pins into las
d and OMA tes
ve.
h 4.7k
Ω – 10kΩ
loys a limiting
s recommende
odule.
3 = 3.14 to 3.46
Typ
Per 802.3ae re
permanently
p
Max
4.0
85
46 Volts)
p
Max
3.46
0
400
0
700
Vcc
Vee+ 0.8
850
VccHOST
Vee+0.8
31 Rev 4.1
ser driver IC.
st pattern. Use
Ω on the host b
receiver. Hos
ed settings for i
6 Volts)
Max
+4.0
1565
3.0
-30
equirements
-128
Page
y.
Unit
R
V
°C
%
Unit
R
V
mA
Ω
mV
V
mV
ps
V
mVpp
of four 1’s and
board. Normal
st board design
interoperating
Unit
Ref
dBm
1
nm
dB
dBm
dB/Hz
3
Ref.
1
1
2,6
3
4
5
d
ers
f.
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