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參數(shù)資料
| 型號(hào)： | FST3126QSCX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 3/5頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SWITCH BUS 4BIT TTL 16-QSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 總線開關(guān) |
| 電路： | 1 x 1:1 |
| 獨(dú)立電路： | 4 |
| 電壓電源： | 單電源 |
| 電源電壓： | 4 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-QSOP |
| 包裝： | 帶卷 (TR) |
3
www.fairchildsemi.com
FST3
126
AC Electrical Characteristics
Note 6: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Capacitance (Note 7)
Note 7: TA = +25°C, f = 1 MHz, Capacitance is characterized but not tested.
AC Loading and Waveforms
Note: Input driven by 50
source terminated in 50
Note: CL includes load and stray capacitance
Note: Input PRR
= 1.0MHz, t
W = 500ns
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
Symbol
Parameter
TA = 40 °C to +85 °C,
CL = 50pF, RU = RD = 500
Units
Conditions
Figure No.
VCC = 4.5 5.5V
VCC = 4.0V
Min
Max
Min
Max
tPHL,tPLH
Prop Delay Bus to Bus (Note 6)
0.25
ns
VI = OPEN
Figures 1, 2
tPZH, tPZL
Output Enable Time
1.0
4.5
5.0
ns
VI = 7V for tPZL
Figures 1, 2
VI = OPEN for tPZH
tPHZ, tPLZ
Output Disable Time
1.5
5.7
6.2
ns
VI = 7V for tPLZ
Figures 1, 2
VI = OPEN for tPHZ
Symbol
Parameter
Typ
Max
Units
Conditions
CIN
Control Pin Input Capacitance
3
pF
VCC = 5.0V
CI/O
Input/Output Capacitance
5
pF
VCC = 5.0V, OE = 0V
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