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參數(shù)資料
| 型號(hào)： | FSAU3157 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Low Voltage SPDT Analog Switch with 2V Undershoot Protection |
| 中文描述： | 低壓?jiǎn)蔚峨p擲模擬開關(guān)，具有2V的下沖保護(hù) |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 180K |
| 代理商： | FSAU3157 |
www.fairchildsemi.com
4
N
DC Electrical Characteristics
(Continued)
Note 7:
Flatness is defined as the difference between the maximum and minimum value of On Resistance over the specified range of conditions.
Note 8:
Guaranteed by Design.
AC Electrical Characteristics
Note 9:
Guaranteed by Design.
Note 10:
This parameter is guaranteed by design but not tested. The bus switch contributes no propagation delay other than the RC delay of the On Resistance of the switch and
the 50 pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Note 11:
Off Isolation 20 log
10
[V
A
/ V
Bn
]
Symbol
Parameter
V
CC
(V)
T
A
25 C
Typ
T
A
40 C to 85 C
Min
Units
Conditions
Figure
Min
Max
Max
Number
t
PHL
t
PLH
Propagation Delay
Bus to Bus
1.65 1.95
2.3 2.7
ns
V
I
OPEN
Figures
2, 3
1.2
1.2
(Note 10)
3.0 3.6
4.5 5.5
1.65 1.95
0.8
0.3
23.0
0.8
0.3
24.0
t
PZL
t
PZH
Output Enable Time
7.0
7.0
ns
Figures
2, 3
Turn on Time
(A to B
n
)
2.3 2.7
3.0 3.6
4.5 5.5
3.5
2.5
1.7
13.0
6.9
5.2
3.5
2.5
1.7
14.0
7.6
5.7
V
I
2 x V
CC
for t
PZL
V
I
0V for t
PZH
t
PLZ
t
PHZ
Output Disable Time
Turn Off Time
(A Port to B Port)
1.65 1.95
2.3 2.7
3.0 3.6
3.0
2.0
1.5
12.5
7.0
5.0
3.0
2.0
1.5
13.0
7.5
5.3
ns
Figures
2, 3
V
I
2 x V
CC
for t
PLZ
V
I
0V for t
PHZ
4.5 5.5
1.65 1.95
2.3 2.7
0.8
0.5
0.5
3.5
0.8
0.5
0.5
3.8
t
B-M
Break Before Make Time
(Note 9)
ns
Figure 4
3.0 3.6
4.5 5.5
5.0
0.5
0.5
0.5
0.5
Q
Charge Injection (Note 9)
7.0
pC
C
L
0.1 nF, V
GEN
0V
R
GEN
0
R
L
50
f 10MHz
Figure 5
3.3
3.0
57.0
OIRR
Off Isolation (Note 11)
1.65 5.5
dB
Figure 6
Xtalk
Crosstalk
1.65 5.5
54.0
dB
R
L
50
f 10MHz
R
L
50
Figure 7
BW
3dB Bandwidth
1.65 5.5
250
MHz
Figure
10
THD
Total Harmonic Distortion
5
0.011
%
R
L
600
0.5 V
P-P
f 20 Hz to 20 KHz
(Note 9)
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